Patents by Inventor Katsuhiko MURATA

Katsuhiko MURATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ESD PROTECTION CIRCUIT
    Publication number: 20150062764
    Abstract: The ESD protection circuit includes a detection controlling circuit that is connected between the power supply line and the grounding line, detects a current flowing through the power supply line and outputs a controlling signal responsive to a result of the detection. The ESD protection circuit includes a protecting nMOS transistor connected to the power supply line at a drain thereof and receives the controlling signal at a gate thereof. The ESD protection circuit includes one stage of PN-junction diode connected to a source of the protecting nMOS transistor at an anode thereof and to the grounding line at a cathode thereof.
    Type: Application
    Filed: March 4, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoki WAKITA, Mitsuhiro YANO, Ryuji NISHIMOTO, Katsuhiko MURATA