Patents by Inventor Katsuhiko Nakai
Katsuhiko Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9303332Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.Type: GrantFiled: September 12, 2012Date of Patent: April 5, 2016Assignee: SILTRONIC AGInventors: Katsuhiko Nakai, Masamichi Ohkubo, Hikaru Sakamoto
-
Patent number: 8961685Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.Type: GrantFiled: November 10, 2011Date of Patent: February 24, 2015Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
-
Patent number: 8872307Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.Type: GrantFiled: September 12, 2012Date of Patent: October 28, 2014Assignee: Siltronic AGInventor: Katsuhiko Nakai
-
Patent number: 8835284Abstract: Annealed wafers having reduced residual voids after annealing and reduced deterioration of TDDB characteristics of an oxide film formed on the annealed wafer, while extending the range of nitrogen concentration contained in a silicon single crystal, are prepared by a method wherein crystal pulling conditions are controlled such that a ratio V/G between a crystal pulling rate V and an average axial temperature gradient G is ?0.9×(V/G)crit and ?2.5×(V/G)crit, and hydrogen partial pressure is ?3 Pa and ?40 Pa. The silicon single crystal has a nitrogen concentration of >5×1014 atoms/cm3 and ?6×1015atoms/cm3, a carbon concentration of ?1×1015 atoms/cm3 and ?9×1015 atoms/cm3, and heat treatment is performed in a noble gas atmosphere having an impurity concentration of ?5 ppma, or in a non-oxidizing atmosphere.Type: GrantFiled: December 5, 2011Date of Patent: September 16, 2014Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
-
Publication number: 20130277809Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.Type: ApplicationFiled: November 10, 2011Publication date: October 24, 2013Applicant: SILTRONIC AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
-
Publication number: 20130273719Abstract: Annealed wafers having reduced residual voids after annealing and reduced deterioration of TDDB characteristics of an oxide film formed on the annealed wafer, while extending the range of nitrogen concentration contained in a silicon single crystal, are prepared by a method wherein crystal pulling conditions are controlled such that a ratio V/G between a crystal pulling rate V and an average axial temperature gradient G is ?0.9×(V/G)crit and ?2.5×(V/G)crit, and hydrogen partial pressure is ?3 Pa and ?40 Pa. The silicon single crystal has a nitrogen concentration of >5×1014 atoms/cm3 and ?6×1015 atoms/cm3, a carbon concentration of ?1×1015 atoms/cm3 and ?9×1015 atoms/cm3, and heat treatment is performed in a noble gas atmosphere having an impurity concentration of ?5 ppma, or in a non-oxidizing atmosphere.Type: ApplicationFiled: December 5, 2011Publication date: October 17, 2013Applicant: SILTRONIC AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
-
Patent number: 8545622Abstract: An annealed wafer in which oxygen precipitation is uniform in the substrate plane and a manufacturing method thereof are provided. A nitrogen-doped silicon single crystal substrate pulled at the cooling rate of 4° C./minute or more during crystal growth between 1100 and 1000° C. wherein the nitrogen concentration is 1×1014 to 5×1015 atoms/cm3 and V/G satisfies predetermined conditions serves as a substrate, and the substrate is subjected to heat treatment in a non-oxidative atmosphere.Type: GrantFiled: December 22, 2006Date of Patent: October 1, 2013Assignee: Siltronic AGInventors: Katsuhiko Nakai, Koji Fukuhara
-
Patent number: 8524001Abstract: Silicon wafers having excellent voltage resistance characteristics of an oxide film and high C-mode characteristics are derived from single crystal silicon ingots doped with nitrogen and hydrogen, characterized in that a plurality of voids constituting a bubble-like void aggregates are present ?50% relative to total voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 is ?20% of the total area of wafer; a V2 region having a void density of 5×102 to 2×104/cm3 occupies ?80% of the total area of the wafer; and bulk microdefect density is ?5×108/cm3.Type: GrantFiled: December 16, 2009Date of Patent: September 3, 2013Assignee: Siltronic AGInventors: Katsuhiko Nakai, Atsushi Ikari, Masamichi Ohkubo
-
Patent number: 8524002Abstract: Silicon wafers doped with nitrogen, hydrogen and carbon, have a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 which occupies 20% or less of the total area of the silicon wafer; a V2 region having a void density of 5×102 to 2×104/cm3 which occupies 80% or more of the total area of said silicon wafer; and a bulk micro defect density which is 5×108/cm3 or more, have excellent GOI characteristics and a high C-mode pass rate. The wafers are cut from a single crystal pulled by a method in which carbon, nitrogen, and hydrogen dopants are controlled, and the crystal is subjected to rapid cooling.Type: GrantFiled: December 20, 2010Date of Patent: September 3, 2013Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
-
Publication number: 20130161793Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.Type: ApplicationFiled: September 12, 2012Publication date: June 27, 2013Applicant: SILTRONIC AGInventors: Katsuhiko Nakai, Masamichi Ohkubo, Hikaru Sakamoto
-
Publication number: 20130093058Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.Type: ApplicationFiled: September 12, 2012Publication date: April 18, 2013Applicant: SILTRONIC AGInventor: Katsuhiko Nakai
-
Patent number: 8382894Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.Type: GrantFiled: October 26, 2009Date of Patent: February 26, 2013Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masayuki Fukuda
-
Patent number: 8357939Abstract: A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 ?m and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.Type: GrantFiled: November 30, 2010Date of Patent: January 22, 2013Assignee: Siltronic AGInventor: Katsuhiko Nakai
-
Patent number: 8343618Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.Type: GrantFiled: December 15, 2009Date of Patent: January 1, 2013Assignee: Siltronic AGInventors: Masayuki Fukuda, Katsuhiko Nakai
-
Patent number: 8241421Abstract: The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: growing a silicon crystal by the Czochralski method comprising adding hydrogen and nitrogen to a silicon melt and growing from the silicon melt a silicon crystal having a nitrogen concentration of from 3×1013 cm?3 to 3×1014 cm?3, preparing a silicon substrate by machining the silicon crystal, and forming an epitaxial layer at the surface of the silicon substrate.Type: GrantFiled: October 1, 2010Date of Patent: August 14, 2012Assignee: Siltronic AGInventors: Katsuhiko Nakai, Timo Mueller, Atsushi Ikari, Wilfried von Ammon, Martin Weber
-
Patent number: 8197594Abstract: Silicon wafers having a density of BMDs with sizes between 20 to 40 nm at positions ?20 ?m below the wafer surface in the range of 5×1011/cm3, and a density of BMDs with sizes of ?300 nm?1×107/cm3, exhibit reduced slip dislocation and warpage. The wafers are sliced from a crystal grown under specific conditions and then subjected to both low temperature heat-treatment and high temperature anneal.Type: GrantFiled: September 19, 2007Date of Patent: June 12, 2012Assignee: Siltronic AGInventors: Katsuhiko Nakai, Wilfried von Ammon, Sei Fukushima, Herbert Schmidt, Martin Weber
-
Patent number: 8142885Abstract: Silicon wafers and a process for their manufacture wherein both slip dislocation and occurrence of warpage are suppressed include heat treatment to provide wafers having plate-shaped BMDs, a density of BMDs whose diagonal lengths are in a range of 10 nm to 120 nm, of BMDs present in the bulk of the wafer at a distance of 50 ?m or more is 1×1011/cm3 or more, and the density of BMDs whose diagonal lengths are 750 nm or more in the wafer bulk is 1×107/cm3 or less, and the interstitial oxygen concentration is 5×1017 atoms/cm3 or less. The process involves low and high temperature heat treating at under defined temperature ramping rates.Type: GrantFiled: November 29, 2007Date of Patent: March 27, 2012Assignee: Siltronic AGInventors: Katsuhiko Nakai, Sei Fukushima
-
Publication number: 20110156216Abstract: Silicon wafers doped with nitrogen, hydrogen and carbon, have a plurality of voids, wherein 50% or more of the total number of voids are bubble-like shaped aggregates of voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 which occupies 20% or less of the total area of the silicon wafer; a V2 region having a void density of 5×102 to 2×104/cm3 which occupies 80% or more of the total area of said silicon wafer; and a bulk micro defect density which is 5×108/cm3 or more, have excellent GOI characteristics and a high C-mode pass rate. The wafers are cut from a single crystal pulled by a method in which carbon, nitrogen, and hydrogen dopants are controlled, and the crystal is subjected to rapid cooling.Type: ApplicationFiled: December 20, 2010Publication date: June 30, 2011Applicant: SILTRONIC AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
-
Publication number: 20110156215Abstract: A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 ?m and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.Type: ApplicationFiled: November 30, 2010Publication date: June 30, 2011Applicant: SILTRONIC AGInventor: Katsuhiko Nakai
-
Patent number: RE45238Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.Type: GrantFiled: February 13, 2013Date of Patent: November 11, 2014Assignee: Siltronic AGInventors: Masayuki Fukuda, Katsuhiko Nakai