Patents by Inventor Katsuhiko Nishitani

Katsuhiko Nishitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150079764
    Abstract: According to one embodiment, a vapor phase growth apparatus includes a susceptor in a chamber, the susceptor configured to rotate on an axis perpendicular to a surface of the susceptor, a plurality of substrate holding portions above the susceptor, each of the substrate holding portions configured to revolve around the axis by the rotation of the susceptor and configured to rotate circumferentially, a plurality of bearings arranged in a housing between the susceptor and the substrate holding portion, and a plurality of blade portions on an outer periphery of the substrate holding portion, each of the blade portions extending radially toward a center of the substrate holding portion.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Katsuhiko Nishitani
  • Patent number: 8729585
    Abstract: According to one embodiment, in a semiconductor light emitting device, a substrate includes a first surface, a second surface opposite to the first surface, lateral surfaces intersected with the first surface and the second surface, first regions each provided on the lateral surface, and second regions each provided on the lateral surface. Each of the first regions has a first width and a first roughness. Each of the second regions has a second width smaller than the first width and a second roughness smaller than the first roughness. The first regions and the second regions are alternately arranged. A proportion of the sum of the first widths to a distance between the first surface and the second surface is 0.5 or more. A semiconductor laminated body is provided above the first surface of the substrate, and includes a first semiconductor layer, an active layer and a second semiconductor layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kimitaka Yoshimura, Katsuhiko Nishitani, Akihiro Fujiwara
  • Publication number: 20130015481
    Abstract: According to one embodiment, in a semiconductor light emitting device, a substrate includes a first surface, a second surface opposite to the first surface, lateral surfaces intersected with the first surface and the second surface, first regions each provided on the lateral surface, and second regions each provided on the lateral surface. Each of the first regions has a first width and a first roughness. Each of the second regions has a second width smaller than the first width and a second roughness smaller than the first roughness. The first regions and the second regions are alternately arranged. A proportion of the sum of the first widths to a distance between the first surface and the second surface is 0.5 or more. A semiconductor laminated body is provided above the first surface of the substrate, and includes a first semiconductor layer, an active layer and a second semiconductor layer.
    Type: Application
    Filed: March 15, 2012
    Publication date: January 17, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kimitaka YOSHIMURA, Katsuhiko NISHITANI, Akihiro FUJIWARA
  • Patent number: 5792698
    Abstract: A method of manufacturing a semiconductor light emitting device employs an MOCVD process. The method sequentially forms, on a GaAs substrate, at least an InGaAlP clad layer, an active layer, an InGaAlP clad layer, a GaAlAs or InGaAlP current diffusion layer, and a GaAlAs or InGaAlP light scattering layer. The flow-rate ratio (V/III ratio) of a V-group source gas to a III-group source gas for forming the light scattering layer is smaller than that for forming the current diffusion layer. As a result, the surface of the light scattering layer is roughened to improve light emission efficiency.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: August 11, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuhiko Nishitani
  • Patent number: 5744828
    Abstract: A semiconductor light emitting device has a semiconductor substrate (1). On a first principal plane of the substrate, an emission layer is formed. In a predetermined region on the emission layer, a current blocking layer (10) is formed. On the current blocking layer, an excitation electrode (20) is formed. A substrate electrode (9) is formed on a second principal plane of the substrate. The excitation electrode is composed of a bonding pad (21) and a current supply electrode (22). The current blocking layer is under the bonding pad. The current blocking layer prevents a current from flowing under the bonding pad. The current supply electrode improves the light emission efficiency of the device.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: April 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Nozaki, Kazumi Unno, Yasuo Idei, Katsuhiko Nishitani