Patents by Inventor Katsuhiko Nishiwaki
Katsuhiko Nishiwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9761681Abstract: The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film. Further, the semiconductor device includes an emitter region of an n-type provided in the semiconductor substrate, exposed on the front surface of the semiconductor substrate, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film provided on the inner surface of the intersection of the first trench and the second trench.Type: GrantFiled: March 27, 2015Date of Patent: September 12, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Katsuhiko Nishiwaki
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Publication number: 20170069729Abstract: The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film. Further, the semiconductor device includes an emitter region of an n-type provided in the semiconductor substrate, exposed on the front surface of the semiconductor substrate, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film provided on the inner surface of the intersection of the first trench and the second trench.Type: ApplicationFiled: March 27, 2015Publication date: March 9, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Katsuhiko NISHIWAKI
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Publication number: 20160005843Abstract: By using an SOI substrate in which a front surface-side semiconductor layer, an insulating layer, and a back surface-side semiconductor layer are laminated in this order, vertical semiconductor devices are mass-produced. A process to be executed on a front surface of the SOI substrate is executed on the front surface. A back surface of the SOI substrate is etched so that the back surface-side semiconductor layer and the insulating layer are removed and a back surface of the front surface-side semiconductor layer is exposed. A process to be executed on the exposed back surface of the front surface-side semiconductor layer is executed on the back surface. A thickness of the front surface-side semiconductor layer of the SOI substrate can be accurately controlled, and the semiconductor devices having a semiconductor layer with the same thickness as the thickness of the front surface-side semiconductor layer are mass-produced.Type: ApplicationFiled: February 12, 2013Publication date: January 7, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yasuhiro HIRABAYASHI, Toru ONISHI, Katsuhiko NISHIWAKI, Jun SAITO
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Patent number: 7579652Abstract: To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode 106, having N+ emitter region 104 and P+ emitter region 100, and controlling conduction between emitter and collector by voltage applied to gate electrode 106, the shape of contact opening 108 contacting emitter (N+ emitter region 104 and P+ emitter region 100) and emitter electrode is formed of curved lines at four corners. Hence, eliminating right-angle apex, hole current from the field region into the emitter electrode after switching off is prevented from concentrating at one point.Type: GrantFiled: June 10, 2004Date of Patent: August 25, 2009Assignee: Toyota Jidosha Kabushiki KaishaInventor: Katsuhiko Nishiwaki
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Publication number: 20060163653Abstract: To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode 106, having N+ emitter region 104 and P+ emitter region 100, and controlling conduction between emitter and collector by voltage applied to gate electrode 106, the shape of contact opening 108 contacting emitter (N+ emitter region 104 and P+ emitter region 100) and emitter electrode is formed of curved lines at four corners. Hence, eliminating right-angle apex, hole current from the field region into the emitter electrode after switching off is prevented from concentrating at one point.Type: ApplicationFiled: June 10, 2004Publication date: July 27, 2006Inventor: Katsuhiko Nishiwaki
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Patent number: 6930353Abstract: It is intended to provide a field-effective-type semiconductor device that can let low ON-resistance and non-excessive short-circuit current go together by effectively using its channel width and prevents device from destruction. In a field-effective-type semiconductor device, a semiconductor region arranged between gate electrodes 106 has stripe-patterned structure consisting of an N+ emitter region 104 and a P emitter region. The P emitter region is constituted by P channel region 103 of low concentration and P+ emitter region 100 of high concentration. The N+ emitter region 104, the P channel region 103, and the P+ emitter region 100 are in contact with the emitter electrode 109. Thereby, a channel width X is limited to the extent that is enough for ON current under normal operation state. That is, low ON-resistance and not excessive short-circuit current can go together in the field-effective-type semiconductor device.Type: GrantFiled: October 29, 2003Date of Patent: August 16, 2005Assignee: Toyota Jidosha Kabushiki KaishaInventors: Katsuhiko Nishiwaki, Tomoyoshi Kushida
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Patent number: 6921941Abstract: It is intended to provide a high withstand voltage field effect type semiconductor device that relaxes electric fields in a semiconductor substrate without thickening thickness of a drift region and achieves withstand-ability against high voltage without sacrificing ON-voltage, switch-OFF characteristics, and miniaturization. A field effective type semiconductor device comprises emitter regions 100, 104 and gate electrodes 106 and the like on a surface (upper surface in FIG. 2), a collector region 101 and the like on the other surface (lower surface in FIG. 2), wherein N? field dispersion regions 111 of low impurity concentration are arranged between P body regions 103 facing to gate electrodes 106 and an N drift region 102 below P body regions 103. Thereby, electric field between collector and emitter is relaxed and high withstand voltage field effect type semiconductor device is realized.Type: GrantFiled: February 13, 2004Date of Patent: July 26, 2005Assignee: Toyota Jidosha Kabushiki KaishaInventors: Katsuhiko Nishiwaki, Tomoyoshi Kushida, Sachiko Kawaji
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Publication number: 20040164349Abstract: It is intended to provide a high withstand voltage field effect type semiconductor device that relaxes electric fields in a semiconductor substrate without thickening thickness of a drift region and achieves withstand-ability against high voltage without sacrificing ON-voltage, switch-OFF characteristics, and miniaturization. A field effective type semiconductor device comprises emitter regions 100, 104 and gate electrodes 106 and the like on a surface (upper surface in FIG. 2), a collector region 101 and the like on the other surface (lower surface in FIG. 2), wherein N− field dispersion regions 111 of low impurity concentration are arranged between P body regions 103 facing to gate electrodes 106 and an N drift region 102 below P body regions 103. Thereby, electric field between collector and emitter is relaxed and high withstand voltage field effect type semiconductor device is realized.Type: ApplicationFiled: February 13, 2004Publication date: August 26, 2004Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Katsuhiko Nishiwaki, Tomoyoshi Kushida, Sachiko Kawaji
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Publication number: 20040084725Abstract: It is intended to provide a field-effective-type semiconductor device that can let low ON-resistance and non-excessive short-circuit current go together by effectively using its channel width and prevents device from destruction. In a field-effective-type semiconductor device, a semiconductor region arranged between gate electrodes 106 has stripe-patterned structure consisting of an N+ emitter region 104 and a P emitter region. The P emitter region is constituted by P channel region 103 of low concentration and P+ emitter region 100 of high concentration. The N+ emitter region 104, the P channel region 103, and the P+ emitter region 100 are in contact with the emitter electrode 109. Thereby, a channel width X is limited to the extent that is enough for ON current under normal operation state. That is, low ON-resistance and not excessive short-circuit current can go together in the field-effective-type semiconductor device.Type: ApplicationFiled: October 29, 2003Publication date: May 6, 2004Applicant: Toyota Jidosha Kabushiki KaishaInventors: Katsuhiko Nishiwaki, Tomoyoshi Kushida
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Patent number: 6518629Abstract: In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate electrodes, and an emitter electrode. Strips of the insulation layer extend in a direction intersecting a direction of extension of the gate electrodes, and form a stripe pattern. The insulation layer curbs extraction of holes into the channel region. Openings in the stripe pattern of the insulation layer form depletion layers.Type: GrantFiled: July 3, 2000Date of Patent: February 11, 2003Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tomoyoshi Kushida, Katsuhiko Nishiwaki
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Patent number: 6509610Abstract: A semiconductor device is formed such that a contact surface between a p-type high-concentration semiconductor region and an n-type high-concentration buffer region assumes a convexo-concave shape. This makes it possible to enlarge an area of the contact surface between the p-type high-concentration semiconductor region and the n-type high-concentration buffer region. As a result, holes are injected into an n-type low-concentration drift region from the p-type high-concentration semiconductor region with higher efficiency and with a less voltage drop between the pn-junction. Thus, effects of conductivity modulation can be achieved sufficiently and the on-resistance and the voltage drop of an IGBT can be lowered.Type: GrantFiled: July 18, 2001Date of Patent: January 21, 2003Assignee: Toyota Jidosha Kabushiki KaishaInventors: Akira Kawahashi, Katsuhiko Nishiwaki
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Publication number: 20020013030Abstract: A semiconductor device is formed such that a contact surface between a p-type high-concentration semiconductor region and an n-type high-concentration buffer region assumes a convexo-concave shape. This makes it possible to enlarge an area of the contact surface between the p-type high-concentration semiconductor region and the n-type high-concentration buffer region. As a result, holes are injected into an n-type low-concentration drift region from the p-type high-concentration semiconductor region with higher efficiency and with a less voltage drop between the pn-junction. Thus, effects of conductivity modulation can be achieved sufficiently and the on-resistance and the voltage drop of an IGBT can be lowered.Type: ApplicationFiled: July 18, 2001Publication date: January 31, 2002Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Akira Kawahashi, Katsuhiko Nishiwaki
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Patent number: D276550Type: GrantFiled: May 17, 1982Date of Patent: November 27, 1984Assignee: Hitachi, Ltd.Inventors: Shuichi Kouno, Katsuhiko Nishiwaki, Kenichi Watanabe
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Patent number: D278712Type: GrantFiled: November 26, 1982Date of Patent: May 7, 1985Assignee: Hitachi, Ltd.Inventors: Koushirou Adachi, Katsuhiko Nishiwaki, Motoake Sakamoto, Tamotsu Tsukaguchi, Mitsuo Miyamoto
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Patent number: D279780Type: GrantFiled: March 24, 1983Date of Patent: July 23, 1985Assignee: Hitachi, Ltd.Inventors: Katsuhiko Nishiwaki, Akitaka Takeuchi, Hiroshi Endo, Akihiro Kawakami, Hideo Matsumura