Abstract: A recording medium recording a packet classification program for causing a computer to perform processing includes: storing, by every one of a plurality of threads, in a case where input packets include identification information of terminals identification information of sessions used for transmitting the input packets, in association with classification categories associated with the terminals and time information in the input packets; specifying, by every one of a plurality of classification threads that performs classification processing of the input packets, in a case where a target packet of the classification processing does not include identification information of a terminal that processes the target packet, classification categories associated with identification information of a session used for transmitting the target packet and a time equal to or earlier than time Information in the target packet; and classifying the target packet into a classification category associated with a relatively later

Abstract: A control device includes a processor. The processor is configured to acquire, from a switch, a flow table that includes flow entries each including a match field that defines processing for a packet and includes at least a destination address. The processor is configured to extract a flow entry that is included in the acquired flow table and includes a match field that matches a match field of an entry of matching information stored in advance in a memory. The processor is configured to generate a pseudo packet corresponding to the extracted flow entry. The processor is configured to transmit the generated pseudo packet to the switch.

Abstract: A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.

Abstract: A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.