Abstract: A non-transitory computer-readable storage medium storing a network map creation support program that causes a processor included in a computer to execute a process, the process includes calculating, for each of a plurality of nodes, an evaluation value indicating a possibility that the node is connected to a target switch port of a plurality of switches based on information indicating measurement results related to communication data of a network including the plurality of nodes and the plurality of switches, or a coupling environment of the plurality of nodes and the plurality of switches in the network, displaying figures respectively representing the plurality of nodes in descending order of the evaluation value starting from a position nearest to a figure representing the target switch port, and receiving a selection of one of the plurality of nodes as a node to be coupled to the target switch port in a network map.

Abstract: A storage apparatus is disclosed, including a first storage area, a second storage area, and a controller. The controller writes data to the first storage area based on a write request. When the data are written in the first storage area, the controller sequentially writes the data to the second storage area from a beginning of a physical address thereof. The controller outputs the data to a backup apparatus by sequentially reading out the data being written in the second storage area from the beginning of the physical address.

Abstract: A prefetch control device controls prefetching of read-out data into cache memory which improves efficiency of data reading from a storage device by caching data passed between the storage device and a computing device, determines whether data read out from the storage device to the computing device is sequentially accessed data or not, decides a prefetch amount for the read-out data in accordance with a predetermined condition if the read-out data is determined to be sequentially accessed data, and prefetches the read-out data of the prefetch amount.

Abstract: A prefetch control apparatus includes a prefetch controller for controlling prefetch of read data into a cache memory caching data to be transferred between a computer apparatus and a storage device, and which enhances a read efficiency of the read data from the storage device, a sequentiality decider for deciding whether the read data that are read from the storage device toward the computer apparatus are sequential access data, a locality decider for deciding whether the read data have locality of data arrangement in the predetermined storage area, in a case where the read data that are read from the storage device toward the computer apparatus have been decided not to be sequential access data, and a prefetcher for prefetching the read data in a case where the read data has the locality of the data arrangement.

Abstract: A shared storage configuration system for use in a computer system includes a plurality of processing modules. Each of the processing modules includes at least a main storage unit, a central processing unit and a connecting unit for connection to a system bus. The shared storage system also includes a plurality of shared storage modules. Each of the shared storage modules includes a shared storage unit and a connection unit for connection to the system bus. A space inherent in the processing modules is accessible by physical addresses of said central processing unit of each of the processing modules. A shared storage space is accessible by the physical addresses of said central processing unit of each of the processing modules.

Abstract: A shared storage configuration system for use in a computer system includes a plurality of processing modules and a plurality of shared storage modules. Each of the processing modules has at least a main storage unit, a central processing unit, and a connection unit for connection to a system bus. Each of the shared storage modules has a shared storage unit and a connection unit for connection to the system bus. A space inherent in the processing modules is accessible by physical addresses of the central processing units. The shared storage space is accessible either in program mode by the physical addresses of the central processing units or in direct memory access mode by relative addresses translated from the physical addresses output by the central processing units.

Abstract: Rush current is dispersed with a power control section having a simple construction, irrespective of the number of disk units. A plurality of disk modules each having a built-in power section and a built-in disk drive are grouped and housed in a single disk unit. A plurality of disk units are provided in response to the system scale. An input/output control section is provided in a disk unit, and performs control of data input/output to and from the plurality of disk modules in the same unit and issuance, upon power-on, of a power-on instruction in compliance with a predetermined procedure. There is provided a first power control section common to all the disk units for instructing power-on in a lump.

Abstract: In a logic unit provided with a plurality of internal registers, an internal memory and a combinational circuit, such as an arithmetic unit, at least one of the plurality of internal registers is arranged to be scanned in and out. During diagnosis, when executing an instruction which makes reference to the internal memory, the register that can be scanned in and scanned out is used in place of the internal memory for diagnosing the combinational circuit.