Abstract: There is disclosed a double gate GTO thyristor having a high gate gain and a high gate sensitivity, and capable of high speed turn-off. The double gate GTO thyristor comprises an anode/emitter layer, first and second base layers and cathode/emitter layer. A semiconductor layer having a conductivity type opposite to that of the anode/emitter layer is formed in the anode/emitter layer and located at a surface portion of the anode/emitter layer. A first gate electrode is connected to the first base layer, and a second gate electrode to the second base layer. An anode electrode is connected to the anode/emitter layer and all the surface of the semiconductor layer. A cathode electrode is connected to the cathode/emitter layer.

Abstract: A gate turn-off thyristor drive system with low power loss when it is in the turn-off mode, is disclosed. A first turn-off pulse of a predetermined amplitude is applied to a first gate electrode. A second turn-off pulse is applied to a second gate electrode. An amplitude of the second turn-off pulse is smaller in absolute value than that of the first turn-off pulse. The fall time of the anode current at the time of turn-off is reduced, and the initial value of the tail current of the anode current is reduced. The power loss as the product of the anode voltage and the anode current is reduced.

Abstract: A reverse conducting gate turn-off thyristor device in which a gate turn-off thyristor and a reverse conduction diode are integrally formed in the same semiconductor wafer is constituted in such a manner that a part of a gate electrode is arranged in an isolation region that is sandwiched by the gate turn-off thyristor section and the reverse conduction diode section.

Abstract: An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.

Abstract: A pressure-applied type semiconductor device, in which a metal stamp for urging a semiconductor body is formed with a peripheral annular groove. When pressure is applied, the groove is elastically deformed. Thus, stress concentration in the semiconductor body directly under the edge of the metal stamp can be alleviated.

Abstract: A protecting device includes a discriminating circuit and a protecting circuit. The GTO thyristor is operated in such a manner that a carrier storing is completed from a first time point at which the supply of a negative gate current is started to a second time point, an anode-cathode voltage increases from the second time point to a third time point and decreases from the third time point to a fourth time point, and increases again from the fourth time point. The discriminating circuit includes a circuit for obtaining an amount of change between the anode-cathode voltages at the third and fourth time points, a circuit for obtaining a ratio of the amount of change to the anode-cathode voltage at the third time point, and a comparing circuit for producing a control signal when the ratio is smaller than a given value. The protecting circuit, when receiving the control signal, stops the conduction of the GTO thyristor.

Abstract: A compression type semiconductor device includes a semiconductor element; at least one metal plate having substantially upright edge surfaces, a planar contacting surface engaging a first surface of the semiconductor element and a continuous curved surface interconnecting the edge surfaces and the contacting surface; and a means for pressing the contacting surface of the metal plate against the first surface of the semiconductor element. The continuous curved surface of the metal plate is so formed that at each point on the periphery of the contacting surface at least one plane normal to the contacting surface intersects the curved surface in an arcuate curve which tangentially joins the contacting surface.

Abstract: A method for manufacturing a semiconductor device having a cathode layer divided into a plurality of mesa type cathode layer portions and used under pressure applied from the cathode layer side through a pressing plate, the method comprising steps of disposing a flat plate having a lateral width covering at least from the outer edge of a cathode electrode disposed on one outermost cathode layer portion to the outer edge of a cathode electrode disposed on the other outermost cathode layer portion, applying an external pressure through the flat plate, and then disposing the pressing plate.