Patents by Inventor Katsuhiko Tamura

Katsuhiko Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030030101
    Abstract: The generation of leakage currents between gate electrodes can be minimized while maintaining the dimensional accuracy and height of the gate electrodes. For example by lamp heating, an oxide film (7) is formed on gate electrodes (4) having a nitride film (8) on their upper surfaces. Thus, even if silicon dust particles are redeposited in between the gate electrodes 4 in a subsequent cleaning process, the generation of leakage currents between the electrodes can be minimized in semiconductor devices. The oxide film (7) is formed only on the side surfaces of the gate electrodes (4), which prevents a decrease in the film thickness in the upper surfaces of the gate electrodes (4) during the process of forming the oxide film (7). Further, there is no need to thicken a gate electrode material film (3) beforehand in order to maintain the height of the gate electrodes (4), which minimizes degradation in dimensional accuracy of the gate electrodes (4).
    Type: Application
    Filed: April 2, 2002
    Publication date: February 13, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Katsuhiko Tamura
  • Publication number: 20020169634
    Abstract: A healthcare system is composed of a healthcare apparatus for obtaining health-related information of a user and a server for creating exercise menu information to be a target for the user to do exercise and advice information for healthcare of a user. The healthcare apparatus transmits the obtained health-related information to the server. The server creates exercise menu information and transmits the created exercise menu information to the healthcare apparatus, before the healthcare apparatus obtains health-related information. Furthermore, after receiving the health-related information, the server creates advice information based on the exercise menu information and the received health-related information, and transmits the created advice information to the healthcare apparatus.
    Type: Application
    Filed: December 24, 2001
    Publication date: November 14, 2002
    Inventors: Kenzo Nishi, Katsuhiko Tamura
  • Patent number: 5633184
    Abstract: A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: May 27, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiko Tamura, Yukari Imai, Naoko Otani
  • Patent number: 5434813
    Abstract: A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: July 18, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiko Tamura, Yukari Imai, Naoko Otani
  • Patent number: 5381032
    Abstract: A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: January 10, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiko Kokawa, Tohru Koyama, Kenji Kusakabe, Katsuhiko Tamura, Yasuna Nakamura
  • Patent number: 5360756
    Abstract: According to a method of manufacturing a semiconductor device, a monocrystal silicon layer can be formed easily without adversely affecting semiconductor elements. In the method of manufacturing the semiconductor device, a first polysilicon layer is formed on a gate oxide film layer on a silicon substrate, and then a resist is formed on a predetermined region of the first polysilicon layer. Using the resist as a mask, anisotropic etching is effected to expose the surface of the silicon substrate. Thereby, it is not necessary to form the resist directly on the gate oxide film layer, as is done in the prior art, and it is possible to prevent impurity such as sodium or phosphorus in the resist from entering the gate oxide film layer. Consequently, it is possible to prevent a disadvantage such as change of a threshold voltage of a memory cell transistor, which may be caused by the entry of impurity.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: November 1, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsuhiko Tamura
  • Patent number: 5338955
    Abstract: A DRAM providing a capacitor capacity sufficient for maintaining stable storage of data even if elements are further reduced in size in accordance with high density integration of semiconductor devices is disclosed. The DRAM has its capacitor upper electrode formed of an upper layer and a lower layer, and its capacitor lower electrode formed to surround the lower layer of the capacitor upper layer, and the upper layer of the capacitor upper layer formed to cover the upper surface and both sides of the capacitor lower electrode. Thus, a capacitor capacity is tremendously increased as compared to a conventional one in the same plane area as the conventional one.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: August 16, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiko Tamura, Atsuko Kawai
  • Patent number: 5221630
    Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: June 22, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Koyama, Katsuhiko Tamura, Yasuna Nakamura, Yoshiko Kokawa, Kenji Kusakabe
  • Patent number: 5177569
    Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: January 5, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Koyama, Katsuhiko Tamura, Yasuna Nakamura, Yoshiko Kokawa, Kenji Kusakabe
  • Patent number: 4778584
    Abstract: Disclosed is a liquid filter device for effectively eliminating impurities from liquid.Voltage is applied to liquid to break electrostatic coupling of liquid molecules and impurity molecules. The impurity molecules are electrostatically adsorbed by an electrode containing adsorbent having charges different in polarity from those of the impurity molecules.Voltage is applied to liquid to break electrostatic coupling of liquid molecules and impurity molecules. Adsorbent having charges different in polarity from those of the impurity molecules on its surface is provided between a pair of electrodes to electrostatically adsorb the impurity molecules. After the impurity molecules are electrostatically adsorbed, the liquid is filtrated by a filter.Voltage is applied to liquid to eliminate zeta potentials which are potential difference at electric double layers having charges different in polarity from those of impurity particles in interfaces between the impurity particles and the liquid.
    Type: Grant
    Filed: June 17, 1986
    Date of Patent: October 18, 1988
    Assignees: Zeotec LRC Corporation, Liquid Concerned Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noboru Inoue, Takaaki Fukumoto, Masaharu Hama, Katsuhiko Tamura, Kimihiko Okaue
  • Patent number: 4765963
    Abstract: A sampled flow of water is extracted from a water conduit 1 carrying impure water by a sampling tube 2, the pressure at a point in the sampling tube is kept constant by a constant pressure maintaining valve 4, and the sampled water passed through a filter 7. The flow rate of sampled water passing through the filter 7 is measured by a flow meter 8. A value corresponding to the total amount or level of impurity in the sampled water is evaluated by an operation circuit 9 at a prescribed time interval, based on the time-dependent change in the result of measurement of the flow meter 8 and the total amount or level of impurities in pure water is thus measured indirectly.
    Type: Grant
    Filed: September 24, 1986
    Date of Patent: August 23, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasukazu Mukogawa, Katsuhiko Tamura, Takaaki Fukumoto