Patents by Inventor Katsuhiko Tanaka

Katsuhiko Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140001030
    Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 2, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Katsuhiko TANAKA
  • Patent number: 8551884
    Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Katsuhiko Tanaka
  • Patent number: 8525555
    Abstract: In a power detector, a comparator for detection receives an input signal and a reference voltage, and compares the input signal to the reference voltage around the switching time of active and inactive states of the output of the comparator in accordance with an output of an input switching signal generator. Except for the switching time, an input voltage for non-use of the comparator is inputs to the comparator for detection, and the differential inputs are fixed to the same potential. Therefore, aging reduction in the accuracy of power detection caused by BT degradation is effectively mitigated.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Kondo, Katsuhiko Tanaka
  • Publication number: 20120302058
    Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.
    Type: Application
    Filed: March 22, 2012
    Publication date: November 29, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Katsuhiko TANAKA
  • Patent number: 8247294
    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: August 21, 2012
    Assignee: NEC Corporation
    Inventors: Kiyoshi Takeuchi, Katsuhiko Tanaka
  • Publication number: 20110097897
    Abstract: A method for manufacturing a semiconductor device, including: forming a barrier seed Ti layer covering a recess in an insulating film; forming a first barrier TiN layer by sputtering; forming a second barrier TiN layer by sputtering with a substrate bias power higher than that in forming the first barrier TiN layer; forming a first wiring seed Ti layer by sputtering; forming a second wiring seed Ti layer by sputtering with a substrate bias power higher than that in forming the first wiring seed Ti layer; forming a first wiring seed Al layer by sputtering; forming a second wiring seed Al layer by sputtering with a substrate bias power higher than that in forming the first wiring seed Al layer; forming Ti—Al alloy in the recess by a heating; and forming an Al wiring material layer so as to fill the recess therewith by sputtering and heating.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 28, 2011
    Applicant: ELPIDA MEMORY, INC
    Inventor: Katsuhiko TANAKA
  • Publication number: 20110059584
    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.
    Type: Application
    Filed: November 15, 2010
    Publication date: March 10, 2011
    Applicant: NEC CORPORATION
    Inventors: Kiyoshi TAKEUCHI, Katsuhiko Tanaka
  • Patent number: 7859065
    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: December 28, 2010
    Assignee: NEC Corporation
    Inventors: Kiyoshi Takeuchi, Katsuhiko Tanaka
  • Patent number: 7830703
    Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: November 9, 2010
    Assignee: NEC Corporation
    Inventors: Koichi Takeda, Masahiro Nomura, Kiyoshi Takeuchi, Hitoshi Wakabayashi, Shigeharu Yamagami, Risho Koh, Koichi Terashima, Katsuhiko Tanaka, Masayasu Tanaka
  • Patent number: 7753538
    Abstract: In a variable-shape mirror provided with a support base, a mirror portion that is disposed to face the support base and that has, on a side thereof facing away from the support base, a mirror surface which is irradiated with a light beam, and piezoelectric elements that are sandwiched between the support base and the mirror portion and that vary the shape of the mirror surface, the piezoelectric elements are bonded, by means of a thin layer of metal, to at least one of the support base and the mirror portion by the application of heat and pressure.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: July 13, 2010
    Assignee: Funai Electric Co., Ltd.
    Inventors: Kenji Nagashima, Hitoshi Fujii, Fuminori Tanaka, Susumu Sugiyama, Akira Ishii, Katsuhiko Tanaka, Wataru Kuze
  • Patent number: 7719043
    Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p
    Type: Grant
    Filed: July 4, 2005
    Date of Patent: May 18, 2010
    Assignee: NEC Corporation
    Inventors: Shigeharu Yamagami, Hitoshi Wakabayashi, Risho Koh, Kiyoshi Takeuchi, Masahiro Nomura, Koichi Takeda, Koichi Terashima, Masayasu Tanaka, Katsuhiko Tanaka
  • Publication number: 20090134454
    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.
    Type: Application
    Filed: June 5, 2006
    Publication date: May 28, 2009
    Applicant: NEC CORPORATION
    Inventors: Kiyoshi Takeuchi, Katsuhiko Tanaka
  • Publication number: 20090014795
    Abstract: A ? gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 15, 2009
    Inventors: Risho Koh, Katsuhiko Tanaka, Shigeharu Yamagami, Koichi Terashima, Hitoshi Wakabayashi, Kiyoshi Takeuchi, Masayasu Tanaka, Masahiro Nomura, Koichi Takeda
  • Publication number: 20090015952
    Abstract: In a variable-shape mirror provided with a support base, a mirror portion that is disposed to face the support base and that has, on a side thereof facing away from the support base, a mirror surface which is irradiated with a light beam, and piezoelectric elements that are sandwiched between the support base and the mirror portion and that vary the shape of the mirror surface, the piezoelectric elements are bonded, by means of a thin layer of metal, to at least one of the support base and the mirror portion by the application of heat and pressure.
    Type: Application
    Filed: September 11, 2008
    Publication date: January 15, 2009
    Applicant: Funai Electric Co., Ltd.
    Inventors: Kenji Nagashima, Hitoshi Fujii, Fuminori Tanaka, Susumu Sugiyama, Akira Ishii, Katsuhiko Tanaka, Wataru Kuze
  • Publication number: 20080289756
    Abstract: A manufacturing method for variable shape mirrors suitable for mass production includes steps: for overlaying a pair of jigs having protruding bar portions like comb teeth on a support substrate so that the protruding bar portions are orthogonal to each other, and inserting support pillars and piezoelectric elements into through hole portions that are formed by gaps between the protruding bar portions, and placing a mirror substrate on the support pillars and the piezoelectric elements; for bonding at least the support substrate and the support pillars, the support substrate and the piezoelectric elements, and the mirror substrate and the support pillars to each other, respectively; for drawing out the jig in the direction opposite to a protruding direction of the protruding bar portion; and for forming a reflection film on an outer surface of the mirror substrate.
    Type: Application
    Filed: August 8, 2007
    Publication date: November 27, 2008
    Inventors: Shigeo Maeda, Katsuhiko Tanaka, Akira Ishii, Susumu Sugiyama
  • Publication number: 20080291559
    Abstract: A variable shape mirror includes a support substrate provided with a conductive bonding portion that is divided into two areas bonded to a lamination type piezoelectric actuator. A bonding surface of the piezoelectric actuator is provided with a first metal film that is divided into a first area and a second area that are not connected to each other electrically. Side faces of the piezoelectric actuator are provided with a second metal film that connects a first common electrode to the first area electrically or connects a second common electrode to the second area electrically. The piezoelectric actuator is disposed on the bonding portion so that the individual areas of the first metal film are connected electrically to the different areas of the bonding portion, respectively.
    Type: Application
    Filed: August 8, 2007
    Publication date: November 27, 2008
    Inventors: Fuminori Tanaka, Katsuhiko Tanaka, Akira Ishii, Susumu Sugiyama
  • Patent number: 7452089
    Abstract: The variable-shape mirror is provided with a support base and a minor portion that is disposed to face the support base and that has on a side thereof facing away from the support base a minor surface which is irradiated with a light beam. There are also provided piezoelectric elements that are sandwiched between the support base and the mirror portion and that vary the shape of the mirror surface. The piezoelectric elements are bonded, through a thin layer of metal that is separately provided for bonding, to at least one of the support base and the mirror portion. A driving voltage to the piezoelectric elements is supplied through the thin layer of metal.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: November 18, 2008
    Assignee: Funai Electric Co., Ltd.
    Inventors: Kenji Nagashima, Hitoshi Fujii, Fuminori Tanaka, Susumu Sugiyama, Akira Ishii, Katsuhiko Tanaka, Wataru Kuze
  • Publication number: 20080278789
    Abstract: In a variable shape mirror including a base substrate; a mirror with a mirror surface; a fixed part, arranged on the base substrate, for fixing the mirror and the base substrate; and an actuator using a piezoelectric ceramics arranged between the base substrate and the mirror; an initial voltage of the actuator is a negative voltage. The initial voltage differs for each actuator; and is larger than or equal to a voltage at which a displacement of the actuator becomes minimum and smaller than zero voltage. The negative initial voltage is a bias voltage, and a voltage stroke is performed while applying the bias voltage.
    Type: Application
    Filed: May 9, 2008
    Publication date: November 13, 2008
    Inventors: Fuminori Tanaka, Shigeo Maeda, Katsuhiko Tanaka, Akira Ishii, Susumu Sugiyama
  • Patent number: 7422335
    Abstract: In a variable-shape mirror of which the shape of the mirror surface can be varied, a mirror portion is bonded only to a fixed portion and not to a piezoelectric element. When the piezoelectric element is not operating, the mirror portion, receiving a predetermined force from the piezoelectric element, makes contact with the piezoelectric element. When the piezoelectric element contracts, the mirror portion tends to restore its original shape by its counterforce. Thus, even when the piezoelectric element contracts, the contact between the mirror portion and the piezoelectric element is held, and hence the electric conduction to the piezoelectric element is maintained.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: September 9, 2008
    Assignee: Funai Electric Co., Ltd.
    Inventors: Hitoshi Fujii, Susumu Sugiyama, Akira Ishii, Katsuhiko Tanaka, Wataru Kuze
  • Patent number: 7390100
    Abstract: A variable-shape mirror is provided with: a support base; a mirror portion that is disposed to face the support base and that has, on a side thereof facing away from the support base, a mirror surface which is irradiated with a light beam; fixed portions that fix the mirror portion to the support base; and piezoelectric elements that are sandwiched between the support base and the mirror portion and that vary a shape of the mirror surface. Here, the piezoelectric elements are arranged closer to a center of the mirror portion than the fixed portions are.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: June 24, 2008
    Assignee: Funai Electric Co., Ltd.
    Inventors: Kenji Nagashima, Hitoshi Fujii, Fuminori Tanaka, Susumu Sugiyama, Akira Ishii, Katsuhiko Tanaka, Wataru Kuze