Patents by Inventor Katsuhiko Tsuura
Katsuhiko Tsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7872327Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: GrantFiled: October 13, 2004Date of Patent: January 18, 2011Assignee: Panasonic CorporationInventor: Katsuhiko Tsuura
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Patent number: 7053495Abstract: A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.Type: GrantFiled: September 16, 2002Date of Patent: May 30, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Katsuhiko Tsuura
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Patent number: 6897541Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: GrantFiled: September 30, 2003Date of Patent: May 24, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Katsuhiko Tsuura
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Publication number: 20050062063Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: ApplicationFiled: October 13, 2004Publication date: March 24, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Katsuhiko Tsuura
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Publication number: 20040061225Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: ApplicationFiled: September 30, 2003Publication date: April 1, 2004Inventor: Katsuhiko Tsuura
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Patent number: 6677195Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: GrantFiled: February 21, 2003Date of Patent: January 13, 2004Assignee: Matsushita Electronics CorporationInventor: Katsuhiko Tsuura
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Publication number: 20030146491Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: ApplicationFiled: February 21, 2003Publication date: August 7, 2003Inventor: Katsuhiko Tsuura
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Patent number: 6562674Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: GrantFiled: June 21, 2000Date of Patent: May 13, 2003Assignee: Matsushita Electronics CorporationInventor: Katsuhiko Tsuura
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Publication number: 20030052440Abstract: A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.Type: ApplicationFiled: September 16, 2002Publication date: March 20, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Katsuhiko Tsuura
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Patent number: 6340604Abstract: Semiconductor chips 15 are separated from one another by cutting a semiconductor wafer along scribing lines, and are fitted in recesses 11 formed in a contactor 10. Bump electrodes 13 are brought into contact with the pad electrodes of the semiconductor chips, so that the former electrodes are electrically connected to the latter electrodes. Each of the recesses of the contactors are surround by side walls which are trapezoid in section. Hence, the side walls can be readily fitted in the grooves formed along the scribing lines; that is, the semiconductors 15 can be fitted in the recesses 11 with ease. The contactor 10 and the dicing sheet having the semiconductor chips 15 are pressed against each other, so that the electrode connection is positively achieved.Type: GrantFiled: December 6, 1999Date of Patent: January 22, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Katsuhiko Tsuura
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Patent number: 6040706Abstract: Semiconductor chips 15 are separated from one another by cutting a semiconductor wafer along scribing lines, and are fitted in recesses 11 formed in a contactor 10. Bump electrodes 13 are brought into contact with the pad electrodes of the semiconductor chips, so that the former electrodes are electrically connected to the latter electrodes. Each of the recesses of the contactors are surround by side walls which are trapezoid in section. Hence, the side walls can be readily fitted in the grooves formed along the scribing lines; that is, the semiconductors 15 can be fitted in the recesses 11 with ease. The contactor 10 and the dicing sheet having the semiconductor chips 15 are pressed against each other, so that the electrode connection is positively achieved.Type: GrantFiled: November 3, 1997Date of Patent: March 21, 2000Assignee: Matsushita Electronics CorporationInventor: Katsuhiko Tsuura