Patents by Inventor Katsuhiko Ueki
Katsuhiko Ueki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947400Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: GrantFiled: May 22, 2023Date of Patent: April 2, 2024Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Publication number: 20230288973Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: ApplicationFiled: May 22, 2023Publication date: September 14, 2023Inventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 11693463Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: GrantFiled: August 1, 2022Date of Patent: July 4, 2023Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 11581052Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.Type: GrantFiled: September 3, 2020Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Akiyoshi Hashimoto, Makoto Kuribara, Takeshi Tomizawa, Katsuhiko Ueki
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Publication number: 20220365577Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Inventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 11435799Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: GrantFiled: August 7, 2020Date of Patent: September 6, 2022Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 11301373Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.Type: GrantFiled: November 30, 2020Date of Patent: April 12, 2022Assignee: KIOXIA CORPORATIONInventors: Daisuke Hashimoto, Shigehiro Asano, Katsuhiko Ueki, Mark Hayashida
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Publication number: 20210295937Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.Type: ApplicationFiled: September 3, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Akiyoshi HASHIMOTO, Makoto KURIBARA, Takeshi TOMIZAWA, Katsuhiko UEKI
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Publication number: 20210081315Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Daisuke HASHIMOTO, Shigehiro ASANO, Katsuhiko UEKI, Mark HAYASHIDA
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Patent number: 10915266Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.Type: GrantFiled: September 16, 2016Date of Patent: February 9, 2021Assignees: TOSHIBA MEMORY CORPORATION, TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATIONInventors: Yusuke Ochi, Masanobu Shirakawa, Yoshihisa Kojima, Kiyotaka Iwasaki, Katsuhiko Ueki, Kouji Watanabe
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Patent number: 10853233Abstract: A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.Type: GrantFiled: October 18, 2016Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Daisuke Hashimoto, Shigehiro Asano, Katsuhiko Ueki, Mark Hayashida
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Publication number: 20200371571Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 10789125Abstract: A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.Type: GrantFiled: April 10, 2019Date of Patent: September 29, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Katsuhiko Ueki, Sumio Kuroda, Yasuyuki Ozawa
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Patent number: 10768679Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: GrantFiled: March 8, 2019Date of Patent: September 8, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 10747449Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.Type: GrantFiled: March 6, 2015Date of Patent: August 18, 2020Assignee: Toshiba Memory CorporationInventors: Tatsuya Zettsu, Katsuhiko Ueki, Yoshihisa Kojima, Hiroshi Yao, Kenichiro Yoshii, Ikuo Magaki
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Patent number: 10410738Abstract: According to one embodiment, a memory system includes a memory, an error correcting circuit and a memory controller. The memory includes a memory cell which is writable in a memory mode including a first mode and a second mode. The first mode is a mode in which a value of bits is written to the memory cell. The second mode is a mode in which a value of bits smaller than that in the first mode is written to the memory cell. The memory controller controls a coding rate for the error correction on the basis of result of error correction. The controller sets the first mode as the memory mode to be used. The controller changes the memory mode to be used from the first mode to the second mode in a case where the coding rate is less than a first threshold.Type: GrantFiled: September 9, 2016Date of Patent: September 10, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsuo Shono, Katsuhiko Ueki
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Patent number: 10402097Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.Type: GrantFiled: September 6, 2018Date of Patent: September 3, 2019Assignee: Toshiba Memory CorporationInventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
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Publication number: 20190235952Abstract: A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventors: Katsuhiko UEKI, Sumio KURODA, Yasuyuki OZAWA
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Patent number: 10365834Abstract: According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.Type: GrantFiled: February 1, 2017Date of Patent: July 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 10347353Abstract: According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.Type: GrantFiled: June 26, 2017Date of Patent: July 9, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Makoto Kuribara, Katsuhiko Ueki, Yoshihisa Kojima