Patents by Inventor Katsuhiko Ueki

Katsuhiko Ueki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10789125
    Abstract: A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiko Ueki, Sumio Kuroda, Yasuyuki Ozawa
  • Patent number: 10768679
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10747449
    Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Zettsu, Katsuhiko Ueki, Yoshihisa Kojima, Hiroshi Yao, Kenichiro Yoshii, Ikuo Magaki
  • Patent number: 10410738
    Abstract: According to one embodiment, a memory system includes a memory, an error correcting circuit and a memory controller. The memory includes a memory cell which is writable in a memory mode including a first mode and a second mode. The first mode is a mode in which a value of bits is written to the memory cell. The second mode is a mode in which a value of bits smaller than that in the first mode is written to the memory cell. The memory controller controls a coding rate for the error correction on the basis of result of error correction. The controller sets the first mode as the memory mode to be used. The controller changes the memory mode to be used from the first mode to the second mode in a case where the coding rate is less than a first threshold.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsuo Shono, Katsuhiko Ueki
  • Patent number: 10402097
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Publication number: 20190235952
    Abstract: A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: Katsuhiko UEKI, Sumio KURODA, Yasuyuki OZAWA
  • Patent number: 10365834
    Abstract: According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10347353
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Kuribara, Katsuhiko Ueki, Yoshihisa Kojima
  • Publication number: 20190204888
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10324788
    Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 18, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichiro Nakazumi, Katsuhiko Ueki, Yoshihisa Kojima
  • Patent number: 10268251
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10261857
    Abstract: A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuhiko Ueki, Sumio Kuroda, Yasuyuki Ozawa
  • Publication number: 20190018596
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10095410
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10042575
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a buffer, a battery and a processing circuit. The battery stores energy supplied from the outside. The processing circuit, after start of the supply of energy from the outside, starts the acceptance of a request from the outside, starts a process in accordance with the accepted request, and restricts the amount of data in the buffer referring to a voltage of the battery. The process uses the buffer.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 7, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Zettsu, Yoshihisa Kojima, Katsuhiko Ueki
  • Publication number: 20180217896
    Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Inventors: Shinichiro Nakazumi, Katsuhiko Ueki, Yoshihisa Kojima
  • Publication number: 20180088828
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.
    Type: Application
    Filed: November 21, 2017
    Publication date: March 29, 2018
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 9928138
    Abstract: According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichiro Nakazumi, Katsuhiko Ueki, Yoshihisa Kojima
  • Publication number: 20180076829
    Abstract: A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 15, 2018
    Inventors: Katsuhiko UEKI, Sumio KURODA, Yasuyuki OZAWA
  • Publication number: 20180059755
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 1, 2018
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki