Patents by Inventor Katsuhiko Wakasugi

Katsuhiko Wakasugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier
    Patent number: 6542424
    Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 1, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hitoshi Endo, Katsuhiko Wakasugi, Youichi Sato, Kazuyoshi Sato
  • Semiconductor integrated circuit device
    Publication number: 20020154562
    Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.
    Type: Application
    Filed: June 18, 2002
    Publication date: October 24, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hitoshi Endo, Katsuhiko Wakasugi, Youichi Sato, Kazuyoshi Sato
  • Semiconductor integrated circuit device
    Patent number: 6452851
    Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: September 17, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hitoshi Endo, Katsuhiko Wakasugi, Youichi Sato, Kazuyoshi Sato