Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Abstract: The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and “1” and “0” are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed.

Abstract: The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and “1” and “0” are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed.

Abstract: The code system is realized by that a plurality of waveforms A and B each having duty ratios of 50% in which only any one of a rising edge and a falling edge is present are combined with each other, and “1” and “0” are allocated to the combined waveform. In accordance with the present invention, both a clock and data can be transmitted at the same time, and can be readily demodulated without using a complex PLL circuit. As a trial manufacture according to the present invention, the demodulator could be realized which could allow variations contained in an input frequency by more than 1 digit under operating voltage of 2 V. The effectiveness of this patent could be confirmed.

Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

Abstract: An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.

Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.

Abstract: A small sized semiconductor device having a high insulating performance between a primary side circuit and a secondary side circuit is realized. A circuit region 2, plural first and second terminal electrodes 5 connected to the circuit region 3, and an insulation-separation region 4 for separating electrically the first terminal electrodes from the second terminal electrodes, and for transmitting signals between the first and the second terminal electrodes are formed onto a semiconductor chip 1, and the insulation-separation region 4 is provided between the first and second terminal electrodes. The interval between the first and the second terminal electrodes on the same semiconductor chip can be separated with high insulating performance.

Abstract: In a digital demodulator for phase modulated signals, logical values of a waveform-shaped phase-modulated signal are sampled based on a clock signal having a period that stands in integer ratio relationship to a carrier period of the modulated signal and thereafter subjected to serial/parallel conversion for each predetermined interval, whereby a logical pattern of a digital code train subjected to the serial/parallel conversion is analyzed. As a result, phase information required to demodulate digital data can be logically detected.

Abstract: A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.

Abstract: An over-sampling analog-to-digital converter using a current switching circuit 102 as a local digital-to-analog converter, wherein a difference between the output currents Isig and Iq of a voltage-to-current converter circuit 101 and a current switching circuit is integrated by a capacitor 105 of which the one end is grounded to a dc potential VB. Further, the current switching circuit 102 has many bits to decrease the difference current between the signal current Isig and the feedback current signal Iq. Moreover, the level-shifting function of the voltage-to-current converter circuit 101 makes it possible to apparently subtract the dc component from the input analog signal Vsig which is produced based on an internally generated dc voltage as a dc bias voltage, and to decrease a change in the voltage between the electrodes of a capacitor caused by the integration of current.

Abstract: A circuit breaker includes a current detector for generator analog voltage signals in accordance with load current of respective phases and a control circuit for executing a tripping operation in response to the analog voltage signals. The control circuit includes an analog switch repeating a time division selecting operation that one of the analog phase voltage signals generated by the current detector is selectively allowed to pass through the same in a predetermined order, an analog-to-digital (A/D) converter for converting the analog voltage signal having passed through the analog switch to a corresponding digital signal, and a microcomputer receiving the digital voltage signal from the A/D converter and obtaining the effective load current value based on the digital voltage signals. The microcomputer generates a tripping order when the effective load current value exceeds a predetermined value.