Patents by Inventor Katsuhiro Hisaka

Katsuhiro Hisaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7429780
    Abstract: A semiconductor device includes a fuse circuit, which includes a first conductive region and a second conductive region. The first conductive region has a multi-layered structure, and the second conductive region has a less layered structure than the first conductive region.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 30, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsuhiro Hisaka
  • Patent number: 7402887
    Abstract: A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the first insulating layer. The diffusion layer is formed on the surface of the semiconductor substrate. The diffusion layer is applied to a fixed potential. The second insulating layer is formed on the fuse. The conductive pattern is formed on the second insulating layer. The conductive pattern surrounds the fuse. Further, the conductive pattern is electrically connected to the diffusion layer.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: July 22, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsuhiro Hisaka
  • Publication number: 20060054992
    Abstract: A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the first insulating layer. The diffusion layer is formed on the surface of the semiconductor substrate. The diffusion layer is applied to a fixed potential. The second insulating layer is formed on the fuse. The conductive pattern is formed on the second insulating layer. The conductive pattern surrounds the fuse. Further, the conductive pattern is electrically connected to the diffusion layer.
    Type: Application
    Filed: March 18, 2005
    Publication date: March 16, 2006
    Inventor: Katsuhiro Hisaka
  • Patent number: 6947268
    Abstract: An ESD-protecting circuit is connected between a terminal pad and an internal circuit formed in an LSI. The ESD-protecting circuit includes a conductive line connected to the terminal pad; first and second protecting elements, connected to the conductive line; and first and second resistive elements formed on the. The conductive line has a slit that divides the conductive line so that the first and second resistive elements have equal resistive values.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: September 20, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsuhiro Hisaka
  • Publication number: 20050067669
    Abstract: A semiconductor device includes a fuse circuit, which includes a first conductive region and a second conductive region. The first conductive region has a multi-layered structure, and the second conductive region has a less layered structure than the first conductive region.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventor: Katsuhiro Hisaka
  • Publication number: 20040224444
    Abstract: A fuse layout (10) constructed of a wiring electrode made of a barrier metal layer of a high melting point and a main wiring metal layer comprises a plurality of fusion-type fuse sections (11 and 12) connected to each other in series and a plurality of fuse pads (13, 14, and 15) for drawing current to the respective fuse sections. If only one of the fuse sections is cut, the whole fuse layout is put in the “cut condition” so that the total fraction defective of incomplete cut of the fuse layout is largely reduced. Even if the barrier metal layer is not cut to remain, it has a high resistance so that the fuse resistance of the whole fuse layout becomes very high and the fuse layout is considered in the “cut condition”.
    Type: Application
    Filed: January 8, 2004
    Publication date: November 11, 2004
    Inventor: Katsuhiro Hisaka
  • Publication number: 20030147188
    Abstract: An ESD-protecting circuit is connected between a terminal pad and an internal circuit formed in an LSI. The ESD-protecting circuit includes first and second conductive lines, connected in parallel to the terminal pad; first and second protecting elements, connected to the first and second conductive lines, respectively; and first and second resistive elements formed on the first and second conductive lines, respectively.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 7, 2003
    Inventor: Katsuhiro Hisaka
  • Patent number: 5334889
    Abstract: An output buffer circuit for use with a power source having first and second power source terminals includes an output terminal, a first transistor connected between the first power source terminal and the output terminal and a second transistor connected between the second power source terminal and the output terminal. A control signal which shifts gradually from the potential at the second power source terminal to the potential at the first power source terminal is applied to the gate of the second transistor. As a consequence, undesirable noises are well suppressed without any substantial degradation in high speed operation.
    Type: Grant
    Filed: February 12, 1992
    Date of Patent: August 2, 1994
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Katsuhiro Hisaka