Patents by Inventor Katsuhiro Kawai

Katsuhiro Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10788817
    Abstract: Provided is a manufacturing process analysis device (30), comprising: a computation unit (31) which computes, in a process in which a manufactured object is manufactured, invariant compliance strengths for each shift time for manufacturing condition values (360) and quality values (361) which are measured in time series; a shift time specification unit (32) which derives, as a specified shift time, a shift time for which the invariant compliance strengths satisfy a baseline; and an analysis unit (33) which analyzes the state of the manufacturing process on the basis of the quality value and the manufacturing condition value for the time which is earlier by the specified shift time than the time at which the quality value is measured.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: September 29, 2020
    Assignee: NEC CORPORATION
    Inventors: Takazumi Kawai, Katsuhiro Ochiai
  • Patent number: 10766120
    Abstract: A method for manufacturing a compressor scroll that appropriately impinges cavitation bubbles on target regions of a scroll. The method includes the step of water jet peening by jetting cavitation bubbles generated underwater by a water jet at a first side of an end plate (13A) of the scroll (13), with a center (P1, P2, P3) of the cavitation bubbles being offset from a center (O) of the spiral shape of a wall portion (13B) on the end plate (13A) and the step portion (13Aa) and the stepped portion (13Ba) positioned at an outer peripheral portion of the cavitation bubbles (C).
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: September 8, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES AUTOMOTIVE THERMAL SYSTEMS CO., LTD.
    Inventors: Takayuki Hagita, Takaharu Maeguchi, Masafumi Hamasaki, Yukio Michishita, Yukihiro Kawai, Hiroshi Ogawa, Makoto Takeuchi, Kazuhide Watanabe, Takayuki Kuwahara, Masaki Kawasaki, Katsuhiro Fujita
  • Publication number: 20200185989
    Abstract: A rotor of a synchronous motor is provided with a plurality of magnets fixed to an outer circumferential surface of a rotor core, and a reinforcement member having a cylindrical shape. An interposition member is disposed between the magnet and the reinforcement member. The magnet includes an outer circumferential surface whose center portion in the circumferential direction bulges outward. The interposition member is formed so as to cover the entire outer circumferential surface of the magnet. An outer circumferential surface of the interposition member has a circular shape when cutting along a plane perpendicular to a rotation axis, and is in close contact with an inner circumferential surface of the reinforcement member.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 11, 2020
    Applicant: Fanuc Corporation
    Inventors: Katsuhiro Saigusa, Takafumi Kajiya, Kenji Kawai
  • Patent number: 6411348
    Abstract: An active matrix is furnished with an insulating substrate; a plurality of scanning lines and signal lines provided on the insulating substrate in a matrix pattern; pixel electrodes provided in areas enclosed by the scanning lines and signal lines, respectively; switching elements electrically connected to the scanning lines, signal lines, and pixel electrodes, respectively; a resistance control element for electrically connecting two lines selected arbitrary from the scanning lines and signal lines while controlling its own resistance value in response to a voltage applied thereto. According to the above arrangement, it has become possible to increase a margin of the active matrix substrate for the static electricity and improve the production yield without increasing the number of the producing steps.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: June 25, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Shinya Yamakawa, Masaya Okamoto, Takayuki Shimada, Mikio Katayama
  • Publication number: 20010045996
    Abstract: An active matrix is furnished with an insulating substrate; a plurality of scanning lines and signal lines provided on the insulating substrate in a matrix pattern; pixel electrodes provided in areas enclosed by the scanning lines and signal lines, respectively; switching elements electrically connected to the scanning lines, signal lines, and pixel electrodes, respectively; a resistance control element for electrically connecting two lines selected arbitrary from the scanning lines and signal lines while controlling its own resistance value in response to a voltage applied thereto. According to the above arrangement, it has become possible to increase a margin of the active matrix substrate for the static electricity and improve the production yield without increasing the number of the producing steps.
    Type: Application
    Filed: June 26, 1997
    Publication date: November 29, 2001
    Inventors: KATSUHIRO KAWAI, SHINYA YAMAKAWA, MASAYA OKAMOTO, TAKAYUKI SHIMADA, MIKIO KATAYAMA
  • Patent number: 6133157
    Abstract: In a method for selectively etching a second silicon layer of a multilayer structure which includes a first silicon layer and the second silicon layer formed on the first silicon layer and doped with impurities according to the present invention, the second silicon layer is selectively etched by using an etching gas including freon-14 gas and a gas selected from a group composed of hydrogen chloride gas and chloride gas.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: October 17, 2000
    Assignee: Sharp Kabushike Kaisha
    Inventors: Takehisa Sakurai, Hitoshi Ujimasa, Katsuhiro Kawai, Atsushi Ban, Masaru Kajitani, Mikio Katayama
  • Patent number: 6091467
    Abstract: An object of the present invention is to attain proper display free from improper display conditions, such as crosstalk, improper contrast and uneven display. Another object is to obtain a high aperture ratio by reducing a margin for bonding. Light shielding films are used to cover the overlap portion of the source electrode and the semiconductor layer and the overlap portion of the drain electrode and the semiconductor layer of a bottom gate type TFT device, such as a staggered type. This structure can suppress off-current due to light leakage, and can prevent deterioration of display quality.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: July 18, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Katsuhiro Kawai, Shinya Yamakawa, Masaya Okamoto
  • Patent number: 6025892
    Abstract: An active matrix substrate of the present invention includes: a substrate; a plurality of first lines formed on the substrate to be parallel to each other; an insulating film covering the first lines; a plurality of second lines formed on the substrate extending to cross the first lines with the insulating film interposed therebetween; a plurality of switching elements provided near respective crossings of the first lines and the second lines; and a plurality of pixel electrodes which are arranged in a matrix on the insulating film and which are connected to the switching elements, respectively. The insulating film is partially removed prior to forming the second lines and the pixel electrodes so that the removed portions of the insulating film correspond to the gaps.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: February 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Shinya Yamakawa, Masaya Okamoto, Mikio Katayama
  • Patent number: 5981972
    Abstract: An active matrix substrate of a Pixel on Passivation structure includes TFTs and pixel electrodes on an interlayer insulating film over bus lines. The interlayer insulating film is formed of an organic insulating film, and the contact layer of the TFT has a double layer structure of a fine crystal silicon (n.sup.+) layer and an amorphous silicon (n.sup.+) layer the crystal silicon (n.sup.+) layer being placed on the side closer to the source electrode and the drain electrode, and the amorphous silicon (n.sup.+) layer being placed on the opposite side. This improves both the ON characteristics and the OFF characteristics of the TFT are improved, and the stable operative region of the active matrix substrate and the margin to accommodate to variations in threshold value due to aging are expanded, without substantial additional production costs and a decrease in productivity.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: November 9, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Shinya Yamakawa, Satoshi Yabuta, Atsushi Ban
  • Patent number: 5962896
    Abstract: A thin film transistor (TFT) has a substrate. There is provided on the substrate a gate electrode, a gate insulating layer, a semiconductor layer, ohmic contact layers, electrodes (i.e., a source electrode and a drain electrode), and a protective layer in this order. An oxidized film is provided on a channel area of the semiconductor layer. With the arrangement, it is possible, without providing a channel protective layer, to prevent undesirable etching to the channel area, thereby greatly reducing the number of defective products. Since it is not necessary to make the semiconductor layer thicker than is required, it is possible to minimize the occurrence that the TFT characteristic is affected by the projected light. In addition, it is possible to realize miniaturization and to get a great aperture ratio when used as a switching element in a liquid crystal display (LCD) device.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: October 5, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Yabuta, Katsuhiro Kawai, Masaru Kajitani
  • Patent number: 5821133
    Abstract: A simplified method of manufacturing an active matrix substrate is disclosed. Gate wires, gate electrodes, gate insulating films, an etching stopper layer, semiconductor layers and contact layers are formed on an electrically insulating substrate. Pixel electrode material films, second electrical conductor films and second insulating films are formed successively on the substrate. The second insulating film and the second electrical conductor film are simultaneously patterned, so that source wires, source electrodes and drain electrodes are formed from the second electrical conductor film, and a protective film from the second insulating film. Then, the pixel electrode material film is patterned thereby to form pixel electrodes in a plurality of regions defined by the gate wires and the source wires.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: October 13, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Mikio Katayama, Satoshi Yabuta, Masaru Kajitani
  • Patent number: 5783494
    Abstract: In a method for selectively etching a second silicon layer of a multilayer structure which includes a first silicon layer and the second silicon layer formed on the first silicon layer and doped with impurities according to the present invention, the second silicon layer is selectively etched by using an etching gas including freon-14 gas and a gas selected from a group composed of hydrogen chloride gas and chlorine gas.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: July 21, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takehisa Sakurai, Hitoshi Ujimasa, Katsuhiro Kawai, Atsushi Ban, Masaru Kajitani, Mikio Katayama
  • Patent number: 5745201
    Abstract: An object of the invention is to facilitate identifying the display color of each pixel during a test process and to apply a correction to a defective switching device in accordance with a test criterion established for each display color. On one transparent substrate, there are formed gate wiring and source wirings intersecting at right angles to each other so that insulation therebetween is maintained, and a pixel electrode and a TFT device are formed for each pixel, thus constructing one substrate member. On another transparent substrate, there is formed a counter electrode facing the pixel electrodes, and identifying means for identifying the display color of each pixel is formed on the side opposite from the side where the counter electrode is formed, the identifying means then being covered with a light-blocking member, thus constructing the another substrate member. The light-blocking member contains openings formed therethrough in portions facing the pixel electrodes.
    Type: Grant
    Filed: October 2, 1996
    Date of Patent: April 28, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Satoshi Yabuta, Masaya Okamoto, Masaru Kajitani
  • Patent number: 5688410
    Abstract: An object of the invention is to enhance the ashing speed of resist. A parallel plate electrode type plasma etching device is used in a mixed gas atmosphere of SF.sub.6 gas and O.sub.2 gas with the concentration of SF.sub.6 gas defined within 5 vol. % to 15 vol. %. A substrate to be treated, coated with a resist of hydrocarbon polymer is placed on a lower electrode. A high frequency electric power is applied to an upper electrode and lower electrode placed parallel to each other, and a plasma of mixed gas is generated in the reactor. A chemical reaction is induced in the resist and active ions of the plasma to vaporize and remove the resist.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: November 18, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaru Kajitani, Satoshi Yabuta, Katsuhiro Kawai, Masaya Okamoto
  • Patent number: 5473168
    Abstract: The thin film transistor of the invention includes a substrate; a gate electrode formed on the substrate; a semiconductor layer insulated from the gate electrode, the semiconductor layer being formed on the substrate to cover the gate electrode; a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 .OMEGA.cm or less, the first and second contact layers being in contact with the semiconductor layer so as cover part of the gate electrode; a source electrode which is in contact with part of the first contact layer; and a drain electrode which is in contact with part of the second contact layer.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: December 5, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Mikio Katayama
  • Patent number: 5287206
    Abstract: An active matrix display device which includes a pair of insulating substrates, a first group of buses formed on one of the sides of the insulating substrates, a second group of buses crossing the first group of buses, conductive film wirings formed on the second group of buses, wherein the width of each conductive film wiring at stepped portions of the first group of buses is not smaller than that of the conductive film wirings located out of the stepped portions.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: February 15, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuzuru Kanemori, Masaya Okamoto, Katsuhiro Kawai, Mitsuaki Hirata, Takehisa Sakurai, Hideji Marumoto
  • Patent number: 5276540
    Abstract: An active matrix substrate which includes a plurality of pixel electrodes arranged in a matrix over an insulating substrate, with each of the pixel electrodes having a transparent conductive film including an additional capacitance portion and a non-additional capacitance portion. Additional capacitance electrodes are capacitively coupled to said additional capacitance portions through at least one insulating film. A conductive film electrically connects the additional capacitance portion to the non-additional capacitance portion of each of the pixel electrodes. The transparent conductive film of each of said pixel electrodes includes a portion for covering the conductive film, the portion for covering having a wider width than a width of the conductive film.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: January 4, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaya Okamoto, Mikio Katayama, Yuzuru Kanemori, Katsuhiro Kawai, Hiroshi Fujiki, Makoto Tachibana
  • Patent number: 4641065
    Abstract: A moving coil type linear motor comprises a rail of generally U-shaped cross section, permanent magnets of flat plate-shape and magnetized in the direction of thickness and provided on an inner side of the rails with varied polarities of magnetic poles next to each other. A pair of coils whose length is 1.5 times that of the magnetic pole and has a space of 0.5 times the length of the magnetic pole in the center thereof, are disposed opposingly with the permanent magnets and travel along the permanent magnets within the rail. Brushes are provided with the respective coils, and a feeder pattern arranged on an inner side of the rail, feeds electric power to the coils through the brushes, only when respective active coil parts of the coils are fully in the magnetic flux of the same direction. The linear motor also comprises sensing means for detecting signals regarding the traveling of the coils, and controlling means for controlling the travel of the coils on the ground of the signals from the sensing means.
    Type: Grant
    Filed: May 14, 1985
    Date of Patent: February 3, 1987
    Assignee: Toyota Shatai Kabushiki Kaisha
    Inventors: Osamu Shibuki, Noboru Matsuyama, Yoshiaki Nagasawa, Katsuhiro Kawai, Shigeru Sakagami, Toshiaki Onoyama