Abstract: Main cells that constitute a semiconductor element having a trench gate structure include first cells, and second cells having a structure in which gate insulating films are more easily broken by energization than those in the first cells, and the number of which is smaller than that of the first cells. At a time of driving the semiconductor element, a common gate drive voltage is applied to gate electrodes of the first cells and the second cells. An electrical characteristic is measured to detect failure of the second cells due to energization at the time of driving. The gate electrodes of the failed second cells are electrically isolated from the gate electrodes of the first cells so that the gate drive voltage is not applied to the failed second cells. The failure of the first cells is predicted based on the failure of the second cells.

Abstract: A state determination device includes an initial waveform storage unit, a waveform acquisition unit, an element temperature acquisition unit, a past waveform storage unit, and a failure state determination unit. The failure state determination unit classifies the time waveform based on the initial time waveform of the gate voltage, the current time waveform of the gate voltage, the element temperature, and the past time waveform of the gate voltage, and determines a fault condition of the IGBT.

Abstract: In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H2SO4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.

Abstract: A manufacturing method of a silicon carbide semiconductor device may include: forming a gate insulating film on a silicon carbide substrate; and forming a gate electrode on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

Abstract: A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.

Abstract: A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ? (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm?2), Q>?*Ec/e.

Abstract: A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

Abstract: A manufacturing method of a silicon carbide semiconductor device may include: forming a gate insulating film on a silicon carbide substrate; and forming a gate electrode on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

Abstract: A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the semiconductor substrate, and an electrode on the interlayer insulating layer. A wide portion and a narrow portion may be arranged alternately between the first and second trenches. The interlayer insulating layer may include a contact hole in the wide portion. The electrode may be in contact with the semiconductor substrate within the contact hole. The semiconductor substrate may include an upper n-type region in contact with the gate insulating layer in the narrow portion and in contact with the electrode, a p-type body contact region in contact with the electrode, a p-type body region in contact with the gate insulating layer in the narrow portion, and a lower n-type region in contact with the gate insulating layer in the narrow portion.

Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.

Abstract: A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the semiconductor substrate, and an electrode on the interlayer insulating layer. A wide portion and a narrow portion may be arranged alternately between the first and second trenches. The interlayer insulating layer may include a contact hole in the wide portion. The electrode may be in contact with the semiconductor substrate within the contact hole. The semiconductor substrate may include an upper n-type region in contact with the gate insulating layer in the narrow portion and in contact with the electrode, a p-type body contact region in contact with the electrode, a p-type body region in contact with the gate insulating layer in the narrow portion, and a lower n-type region in contact with the gate insulating layer in the narrow portion.

Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.

Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.

Abstract: A semiconductor device includes a semiconductor substrate including a trench, a gate insulating layer, and a gate electrode. A step is arranged in a side surface of the trench. The semiconductor substrate includes first and second regions, a body region, and a side region. The body region extends from a position being in contact with the first region to a position located on the lower side with respect to the step. The body region is in contact with the gate insulating layer at a portion of the upper side surface located on a lower side with respect to the first region. The second region is located on a lower side of the body region and in contact with the gate insulating layer at the lower side surface. The side region is in contact with the gate insulating layer at the step surface and connected to the second region.

Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.

Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.

Abstract: An insulated gate type switching device includes: a first region being of a first conductivity type; a body region being of a second conductivity type and in contact with the first region; a second region being of the first conductivity type and separated from the first region by the body region; an insulating film being in contact with the first region, the body region and the second region; and a gate electrode facing the body region via the insulating film. The body region includes a first body region and a second body region. The first body region has a theoretical threshold level Vth larger than that of the second body region.

Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.