Patents by Inventor Katsuhiro KUTSUKI

Katsuhiro KUTSUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10326015
    Abstract: A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the semiconductor substrate, and an electrode on the interlayer insulating layer. A wide portion and a narrow portion may be arranged alternately between the first and second trenches. The interlayer insulating layer may include a contact hole in the wide portion. The electrode may be in contact with the semiconductor substrate within the contact hole. The semiconductor substrate may include an upper n-type region in contact with the gate insulating layer in the narrow portion and in contact with the electrode, a p-type body contact region in contact with the electrode, a p-type body region in contact with the gate insulating layer in the narrow portion, and a lower n-type region in contact with the gate insulating layer in the narrow portion.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masatoshi Tsujimura, Katsuhiro Kutsuki, Sachiko Aoi, Yasushi Urakami
  • Patent number: 10170470
    Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 1, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toru Onishi, Katsuhiro Kutsuki, Yasushi Urakami, Yukihiko Watanabe
  • Patent number: 10141411
    Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 27, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Atsushi Onogi, Toru Onishi, Shuhei Mitani, Yusuke Yamashita, Katsuhiro Kutsuki
  • Publication number: 20180240906
    Abstract: A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the semiconductor substrate, and an electrode on the interlayer insulating layer. A wide portion and a narrow portion may be arranged alternately between the first and second trenches. The interlayer insulating layer may include a contact hole in the wide portion. The electrode may be in contact with the semiconductor substrate within the contact hole. The semiconductor substrate may include an upper n-type region in contact with the gate insulating layer in the narrow portion and in contact with the electrode, a p-type body contact region in contact with the electrode, a p-type body region in contact with the gate insulating layer in the narrow portion, and a lower n-type region in contact with the gate insulating layer in the narrow portion.
    Type: Application
    Filed: December 27, 2017
    Publication date: August 23, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masatoshi TSUJIMURA, Katsuhiro KUTSUKI, Sachiko AOI, Yasushi URAKAMI
  • Publication number: 20180114789
    Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.
    Type: Application
    Filed: August 23, 2017
    Publication date: April 26, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toru ONISHI, Katsuhiro KUTSUKI, Yasushi URAKAMI, Yukihiko WATANABE
  • Patent number: 9847414
    Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: December 19, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Shinichiro Miyahara, Katsuhiro Kutsuki, Sachiko Aoi
  • Publication number: 20170271457
    Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.
    Type: Application
    Filed: February 17, 2017
    Publication date: September 21, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Atsushi ONOGI, Toru ONISHI, Shuhei MITANI, Yusuke YAMASHITA, Katsuhiro KUTSUKI
  • Publication number: 20160149029
    Abstract: A semiconductor device includes a semiconductor substrate including a trench, a gate insulating layer, and a gate electrode. A step is arranged in a side surface of the trench. The semiconductor substrate includes first and second regions, a body region, and a side region. The body region extends from a position being in contact with the first region to a position located on the lower side with respect to the step. The body region is in contact with the gate insulating layer at a portion of the upper side surface located on a lower side with respect to the first region. The second region is located on a lower side of the body region and in contact with the gate insulating layer at the lower side surface. The side region is in contact with the gate insulating layer at the step surface and connected to the second region.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 26, 2016
    Inventors: Hidefumi TAKAYA, Katsuhiro KUTSUKI, Sachiko AOI, Shinichiro MIYAHARA
  • Publication number: 20160141409
    Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 19, 2016
    Inventors: Hidefumi Takaya, Shinichiro Miyahara, Katsuhiro Kutsuki, Sachiko Aoi
  • Patent number: 9281396
    Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 8, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Katsuhiro Kutsuki
  • Publication number: 20160064550
    Abstract: An insulated gate type switching device includes: a first region being of a first conductivity type; a body region being of a second conductivity type and in contact with the first region; a second region being of the first conductivity type and separated from the first region by the body region; an insulating film being in contact with the first region, the body region and the second region; and a gate electrode facing the body region via the insulating film. The body region includes a first body region and a second body region. The first body region has a theoretical threshold level Vth larger than that of the second body region.
    Type: Application
    Filed: August 20, 2015
    Publication date: March 3, 2016
    Inventors: Masahiro Sugimoto, Katsuhiro Kutsuki, Sachiko Aoi, Yukihiko Watanabe, Yasuhiro Ebihara
  • Publication number: 20150129957
    Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.
    Type: Application
    Filed: October 2, 2014
    Publication date: May 14, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi TAKAYA, Katsuhiro KUTSUKI