Abstract: In a listening comprehension test using individual examination execution devices, according to the present invention, it is possible to avoid a dishonest act such as peeping at another examinee's answers. An individual examination execution device (101) reads examination question data and individual information from an examination question storage means (102) storing the examination questions and an individual information storage means (103) storing the individual information, respectively. Further, the individual examination device selectively generates actual questions according to the individual information read by an actual question generation means (104), and reproduces the actual questions by a reproduction means (105), thereby preventing dishonest acts of respective examinees.

Abstract: A processor integrated circuit according to the present invention comprises low-speed and high-speed computing units (110), (120) as two or more kinds of computing units, a program memory (131) as a first storage unit in which programs for operation the computing units are stored, a data memory (second storage unit) (132) as a memory area to be used for computation by the computing units, and selectors (141), (142) as first and second connection switching units for connecting a computing unit that performs computation to the first and second storage units, wherein the program memory (131) and the data memory (132) are connected to the low-speed computing unit (110) or the high-speed computing unit (120). In this construction, it is possible to achieve both of securing in program compatibility and speeding-up without increasing the circuit scale and power consumption of the processor integrated circuit.

Abstract: In a listening comprehension test using individual examination execution devices, it is possible to avoid a dishonest act such as peeping at another examinee's answers. In an individual examination execution device (101), examination question data and individual information are read from an examination question storage means (102) that stores the examination questions and an individual information storage means (103) that stores the individual information, respectively, and actual questions that are selectively generated according to the individual information read by an actual question generation means (104) are reproduced by a reproduction means (105), thereby preventing dishonest acts of the respective examinees.

Abstract: An individual examination execution device is provided with a question storage means (14) in which exam questions are stored, a sequence data holding means (12) that holds sequence data as a basis of exam question reproduction sequence, at sequence instruction means (13) for reading the exam questions stored in the question storage means (14), and a reproduction means (15) for reproducing the exam questions stored in the question storage means (14) into audio. The sequence instruction means (13) reads the exam questions stored in the question storage means (14) with reference to the sequence data stored in the sequence data holding means (12), and the exam question reproduction sequence is changed according to the seat position.

Abstract: A processor integrated circuit according to the present invention comprises low-speed and high-speed computing units (110), (120) as two or more kinds of computing units, a program memory (131) as a first storage unit in which programs for operation the computing units are stored, a data memory (second storage unit) (132) as a memory area to be used for computation by the computing units, and selectors (141), (142) as first and second connection switching units for connecting a computing unit that performs computation to the first and second storage units, wherein the program memory (131) and the data memory (132) are connected to the low-speed computing unit (110) or the high-speed computing unit (120). In this construction, it is possible to achieve both of securing in program compatibility and speeding-up without increasing the circuit scale and power consumption of the processor integrated circuit.

Abstract: There is provided a semiconductor integrated circuit device (100) for downloading a program of an arithmetic processing unit, such as a DSP or a CPU, from the outside, wherein a rewrite program as secret information not to be leaked to third parties, which is downloaded in a semiconductor integrated circuit (109), is checked as to whether it is correctly downloaded or not while maintaining the confidentiality of the rewrite program. The semiconductor integrated circuit device is provided with a circuit for verifying the contents of the downloaded rewrite program, and/or a program for verifying the contents of the downloaded rewrite program.

Abstract: A semiconductor IC 1 is provided with an address input terminal 3 to which addresses for reading secret data stored in the semiconductor IC are supplied from the outside; an input terminal 7 to which a switching control signal C1 for selecting the addresses inputted to the address input terminal 3 is supplied; an arithmetic circuit 6 for performing an arithmetic operation according to a predetermined secret rule on secret data D1˜Dm which are read out; and a test output terminal 8 for outputting results E1˜Ek of the arithmetic circuit 6 to the outside of the semiconductor IC 1. Therefore, the secret data D1˜Dm can easily be read to the outside when the semiconductor IC 1 is subjected to a test or the like, while maintaining confidentiality of the secret data.

Abstract: A video display monitor, such as a plasma monitor, which uses a subfield method which overlaps weighted multiple binary video images in a time base for display. The stable driving of a plasma display panel may be assured and display in the 256 grey-level may be maintained although vertical synchronizing frequency of the input video signal changes. A vertical synchronizing measurement unit measures the vertical synchronizing frequency of the video signal, and a subfield number adjustment unit adjusts the number of subfields in accordance with a measured vertical synchronizing frequency. The stable driving of the plasma display panel and display in grey levels may be assured by selecting a ROM table with an output bit width equivalent to the number of subfields to be output from multiple ROM tables used for converting the number of bits in the input signal.