Abstract: Disclosed is an error correction system in which part of the data bits of first multilevel input data is differentially encoded to form second data comprising the differentially encoded data bits and the remainder data bits and converting the bit patterns of the second data into third data in two-dimensional multilevel signal space according to a predetermined transfer function. A transparent error-correcting code is derived from each of the different phases of the third data and appended to each different phase to thereby form fourth data which is then modulated upon a carrier in two-dimensional multilevel signal space for transmission to a receiver where the signal is demodulated to recover the fourth data. The appended error-correcting code is separated from each different phase of the fourth data. An error which might exist in the received data is corrected by the separated error-correcting code in respect of each phase.

Abstract: A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.

Abstract: An encrypting device for an input data bit sequence comprises a shift register for producing a bit pattern represented by successive encrypted bits for the data bits preceding a current bit. A bit pattern converter selects in compliance with the bit pattern a bit of a code pattern preset therein. A keying bit may be provided by the selected bit, to which the current bit is added modulo two to produce a new encrypted bit. For more excellent encryption, the successively selected bits may be used to produce an additional bit pattern, responsive to which either the keying bit or an additional keying bit, to be also added to the current bit, may be provided by a selected bit of another code pattern. Each bit pattern converter may be preset with a plurality of code patterns. One or more encrypting devices may be used in encrypting a sequence of input data digits, each comprising a plurality of input data bits among which at least one bit may be a dummy bit.

Abstract: An error correcting system for DPSK is comprised of an encoder unit, a decoder unit and a transmission medium disposed between the encoder and decoder units. The encoder includes a differential encoder for differentially encoding an input data sequence, an error correcting encoder for adding a check digit sequence to the differentially encoded data sequence, and a differential decoder for differentially decoding the data sequence added with the check digit sequence. The decoder unit includes a differential encoder for differentially encoding a received data sequences, an error correcting decoder for correcting error digits contained in the differentially encoded received data sequence, and a differential decoder for differentially decoding the output data sequence from the error correcting decoder. The transmission medium typically includes a differentially encoded phase-shifting-keying modulator unit and a differentially encoded phase-shift-keying demodulator unit.

Abstract: A parallel-processing error correction system for digital data transmission employing a code-polynomial division circuit having a serial-type shift register for a cyclic code. Provided with null input lines, one for each data input line, a set of switches for selection between the data and null input lines, and another set of switches associated with buffer registers for series connection therebetween, the device can be readily adapted for any change in number of parallel input bits by switch operation.