Abstract: A first relational expression representing a relationship among gate bias Vd, carrier mobility ?, electric effective channel length Leff and transconductance Gm, and a second relational expression representing a relationship among maximum-transconductance ratio Gmmax L=Lref/Gmmax L=Ltar between a target transistor and a reference transistor and electric effective channel lengths Leff and Lref of the respective transistors are used. Maximum transconductance Gmmax obtained when gate bias Vd is changed is determined and electric effective channel length Leff is estimated by substituting the value of maximum transconductance Gmmax in the second relational expression. The correlation between 1/Gmmax and Lgsem is strong enough to allow maximum transconductance Gmmax to be used in monitoring a process variation of a physical gate length.

Abstract: A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

Abstract: It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4?) are selectively formed in a surface of a body region (16), and extension regions (5) and (5?) are extended from tip portions of the source-drain regions (4) and (4?) opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4?) including the extension regions (5) and (5?) and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6?) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5?) and a peripheral portion of the extension region (5).

Abstract: A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

Abstract: It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4′) are selectively formed in a surface of a body region (16), and extension regions (5) and (5′) are extended from tip portions of the source-drain regions (4) and (4′) opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4′) including the extension regions (5) and (5′) and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6′) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5′) and a peripheral portion of the extension region (5).

Abstract: This invention is to realize a final circuit by wiring only the top layer depending on the individual circuits, by fabricating a master slice in the step of up to forming plural semiconductor elements such as transistors on a semiconductor substrate, forming a lower layer of versatile wiring pieces thereon, and forming contact holes thereon. In this way, since the step just before formation of the top layer wiring can be carried out regardless of the features of individual circuits, preliminary mass productions are possible, and final products can be completed only by forming the wiring of the top layer depending on the requirements of the users. Accordingly, it is applicable to a wide variety of products, and the term for development and manufacture can be tremendously shortened.