Abstract: An end-to-end delay acquisition unit in a radio terminal measures end-to-end delay time, which is the delay time required for end-to-end transmission and reception, by using PING packets in an IP network or the time stamp function of RTCP during VoIP communication. An activation period modification determination module that is provided in the radio terminal modifies the activation period of the radio communication module that carries out radio communication such that the end-to-end delay time that has been measured by the end-to-end delay acquisition unit is equal to or less than a standard value that has been stipulated in advance.

Abstract: A brush holding apparatus is mounted to an inner wall surface of a rear bracket and a cap mounted to a head portion of a brush holder portion is exposed through an opening in the rear bracket. Brushes are housed inside brush insertion apertures of the brush holder portion and are placed in elastic contact with slip rings by springs. An abrasion detection terminal is insert molded into the brush holder portion, a contact thereof projecting inside one of the brush insertion apertures and coming into contact with the corresponding spring when the brushes are abraded by a predetermined amount.

Abstract: A vehicle AC-generator controller includes a storage battery to be charged by a rectification output of an AC generator having a field coil, a voltage regulator for controlling an output voltage of the AC generator to a predetermined value by controlling a field current flowing through the field coil, an indicator lamp for indicating a power-generation state and a no-power generation state of the AC generator, an indicator-lamp driving element for turning on and off the indicator lamp, a power-supply driving element for driving power supply of the voltage regulator in accordance with a turn-on-lamp output of the indicator-lamp driving element, and a power-supply cutoff element for cutting off the power-supply driving apparatus by controlling the turn-on-lamp output to the ground potential when the AC generator is brought into the no-power-generation state.

Abstract: On converting an input data signal having a first transmission rate into an output data signal having a second transmission rate different from the first transmission rate, the input data signal is memorized as a memorized input data signal a first memory. A read clock generating circuit generates a read clock signal to read the memorized input data signal as a read data signal out of the first memory. A read control circuit controls the read clock generating circuit to stop generation of the read clock signal in order to make the read data signal have an overhead bit slot at a predetermined period. A rate control circuit produces a rate control signal having a predetermined pattern and an inhibit signal in accordance with the rate control signal. The read clock generating circuit stops generation of the read clock signal in response to the inhibit signal. A multiplexing circuit multiplexes an information signal to the read data signal on the basis of the rate control signal to produce the output data signal.

Abstract: With the assumption of the bit number of one frame of a synchronous transport module to be S and the bit number of one radio frame in radio communication to be M, the bit number M of the radio frame is set to satisfy a relation S=K.M (K is a natural number other than 0). Hereby, the circuit construction of a SDH radio communiaction transmitter/receiver equipment is simplified and power consumption is reduced. In the case where a radio intermediate switching station is installed, the circuit construction of the intermediate station is simplified and power consumptuion is reduced.

Abstract: An error ratio detector according to the present invention, which detects the error ratio of error correction-coded data with a syndrome, reduces the error pulse occurrence probability by using only the errors in an M (<N) period within each block (of N bits) as errors for calculating the error ratio, and thereby makes it possible to assess the bit error ratio in a high BER region even where blocks are rather long.

Abstract: An apparatus for diagnosing the residual charge of a battery mounted in a vehicle which utilizes an engine includes a comparator for comparing the terminal voltage of the battery with a reference voltage, a stoppage detecting circuit for detecting that the operation of the engine has stopped, a timer for determining that a predetermined time has elapsed since the stoppage detecting circuit detected that the operation of the engine stopped, and a determination circuit for determining the residual charge of the battery from the comparison result provided by the comparator when the timer determined that the predetermined time has elapsed.

Abstract: A digital signal transmission system includes a transmit terminal which as an input interface circuit, a synchronous conversion circuit, a synchronous conversion circuit, a parity check circuit, a multiplex circuit for multiplexing a synchronized input signal with at least a parity check signal, a transmitter and antenna. A fault detector circuit of the transmit terminal detects faults in the input interface stage. The outputs of the fault detector circuit and the parity check circuit are input to a parity check signal output circuit which operates to invert the logical state of the output of the parity check circuit when a fault is detected. A digital signal reception system includes a receive terminal, which has a demultiplex circuit, a frame synchronization circuit, a parity check circuit, a synchronous conversion circuit, an output inface circuit, a receiver and antenna. The transmitted parity check signal is recovered from the demultiplex circuit.

Abstract: A multiplexer includes first and second frequency dividers and first and second selectors. The first frequency divider receives a clock signal which determines a multiplexing time slot and outputs a first signal every M (M.gtoreq.2) time slots. The second frequency divider receives the first signal from said first frequency divider and outputs N (N.gtoreq.1) second signals having different phases. The first selector converts N insertion codes such as a frame synchronization code and a service code into one code signal train on the basis of the second signals. The second selector receives a digital data signal train having an alternate repetition of a digital data signal using (M-1) continuous time slots and a gap of one time slot and inserts the insertion codes of the code signal train on the basis of the first signal.

Abstract: An over current of an output transistor circuit of a voltage regulation of a vehicle mounted charging generator due to a short-circuit of a field winding thereof is detected and a capacitor is charged when the detected current is larger than a predetermined value. The voltage of the capacitor is compared with a reference voltage and the output transistor circuit is cut off during the voltage of the capacitor is larger than the reference voltage, whereby a breakdown of the output transistor circuit is prevented.