Patents by Inventor Katsuhiro Suma
Katsuhiro Suma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070257313Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: May 2, 2007Publication date: November 8, 2007Applicant: Renesas Technology Corp.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 7242060Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: January 18, 2006Date of Patent: July 10, 2007Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20070052028Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: September 19, 2006Publication date: March 8, 2007Applicant: Renesas Technology Corp.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 7138684Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: July 20, 2004Date of Patent: November 21, 2006Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20060118849Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: January 18, 2006Publication date: June 8, 2006Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20050001254Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: July 20, 2004Publication date: January 6, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 6787853Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.Type: GrantFiled: June 23, 2003Date of Patent: September 7, 2004Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 6768662Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: April 24, 2003Date of Patent: July 27, 2004Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20040067614Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.Type: ApplicationFiled: June 23, 2003Publication date: April 8, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20030206472Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: April 24, 2003Publication date: November 6, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 6586803Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.Type: GrantFiled: August 9, 1999Date of Patent: July 1, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 6577522Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: March 12, 2002Date of Patent: June 10, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20020101754Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: March 12, 2002Publication date: August 1, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 6384445Abstract: A semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in the row direction on the SOI substrate. The plurality of bit line pairs are disposed in the column direction on the SOI substrate. The plurality of memory cells are located on the SOI substrate and each are disposed correspondingly to one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a transistor. The transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential.Type: GrantFiled: May 7, 1999Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Takahiro Tsuruda, Katsuhiro Suma
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Patent number: 6385159Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: March 26, 2001Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20020047157Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.Type: ApplicationFiled: August 9, 1999Publication date: April 25, 2002Inventors: HIDETO HIDAKA, KATSUHIRO SUMA, TAKAHIRO TSURUDA
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Patent number: 6288949Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: February 7, 2000Date of Patent: September 11, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Publication number: 20010014047Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: ApplicationFiled: March 26, 2001Publication date: August 16, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Patent number: 6215141Abstract: In manufacturing a semiconductor device, the thickness of source and drain regions is maintained equal by performing the same number of etching steps on each source and drain region. This procedure can be applied to various types of semiconductor devices, such as a memory cell transistor of a DRAM, stack-type memory cell transistor of a DRAM, a peripheral circuit of a DRAM, a semiconductor device formed on an SOI structure, and a trench-type memory cell of a DRAM formed on an SOI structure. By maintaining the source and drain regions at the same thickness, the resistance values are maintained, thereby avoiding deterioration of the transistor characteristics.Type: GrantFiled: June 17, 1996Date of Patent: April 10, 2001Assignee: Mitsubhishi Denki Kabsuhiki KaishaInventors: Hideto Hidaka, Takahiro Tsuruda, Katsuhiro Suma
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Patent number: 6091647Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.Type: GrantFiled: September 2, 1998Date of Patent: July 18, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda