Patents by Inventor Katsuhiro TAKAO

Katsuhiro TAKAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187405
    Abstract: A semiconductor device includes: a semiconductor element having a first electrode and a second electrode on a first surface, and a third electrode on a second surface, wherein continuity between the second electrode and the third electrode is controlled by a voltage applied to the first electrode; a conductive first lead that is electrically connected to the first electrode and extends beyond a periphery of the first surface; and a conductive second lead that is electrically connected to the second electrode and extends beyond the periphery of the first surface. At least one edge of the periphery of the first surface faces neither the first lead nor the second lead, and portions of the first lead and the second lead that face the periphery of the first surface are provided with respective grooves.
    Type: Application
    Filed: July 13, 2020
    Publication date: June 15, 2023
    Inventors: Katsuhiro TAKAO, Atsushi KUROHA
  • Publication number: 20220216135
    Abstract: A semiconductor device includes at least one first semiconductor element having a first electrode, a second semiconductor element having a second electrode, a first lead terminal connected to the first electrode of the at least one first semiconductor element, a second lead terminal connected to the second electrode of the second semiconductor element, a first resin with which the first lead terminal and the second lead terminal are sealed, and a second resin with which the at least one first semiconductor element and the second semiconductor element are sealed.
    Type: Application
    Filed: September 25, 2019
    Publication date: July 7, 2022
    Inventors: Katsuhiro TAKAO, Takashi SUZUKI
  • Patent number: 11075180
    Abstract: A semiconductor device includes a semiconductor element having a plated portion on a part of a main surface and a protective member that seals surfaces of the semiconductor element except for the main surface, wherein the plated portion is electrically connected to a circuit in the semiconductor element.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 27, 2021
    Assignee: AOI Electronics Co., Ltd.
    Inventor: Katsuhiro Takao
  • Publication number: 20210143113
    Abstract: A semiconductor device includes a semiconductor element having a plated portion on a part of a main surface and a protective member that seals surfaces of the semiconductor element except for the main surface, wherein the plated portion is electrically connected to a circuit in the semiconductor element.
    Type: Application
    Filed: August 4, 2017
    Publication date: May 13, 2021
    Inventor: Katsuhiro TAKAO
  • Publication number: 20210050285
    Abstract: A semiconductor device includes: a semiconductor element; an element conductor having an element mounting surface on which the semiconductor element is mounted; a connection conductor that is arranged apart from the element conductor and has a connection surface on an upper part thereof; a connecting line connecting the semiconductor element and the connection surface of the connection conductor; and an encapsulation resin that encapsulates the semiconductor element, the element conductor, the connection conductor, and the connecting line, wherein: a parasitic capacitance reducing structure is provided in at least one of facing side surfaces of the element conductor and of the connection conductor, the facing side surfaces being arranged to face each other.
    Type: Application
    Filed: July 12, 2018
    Publication date: February 18, 2021
    Inventor: Katsuhiro TAKAO
  • Patent number: 10854557
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 1, 2020
    Assignees: AOI Electronics Co., Ltd., Mitsubishi Electric Corporation
    Inventors: Shuichi Sawamoto, Koji Iwabu, Katsuhiro Takao, Akihito Hirai, Joichi Saito
  • Patent number: 10854560
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 1, 2020
    Assignees: AOI Electronics Co., Ltd., Mitsubishi Electric Corporation
    Inventors: Shuichi Sawamoto, Koji Iwabu, Katsuhiro Takao, Akihito Hirai, Joichi Saito
  • Publication number: 20190326227
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Shuichi SAWAMOTO, Koji IWABU, Katsuhiro TAKAO, Akihito HIRAI, Joichi SAITO
  • Publication number: 20180197822
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Application
    Filed: May 19, 2016
    Publication date: July 12, 2018
    Inventors: Shuichi SAWAMOTO, Koji IWABU, Katsuhiro TAKAO, Akihito HIRAI, Joichi SAITO