Patents by Inventor Katsuhiro Torii
Katsuhiro Torii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9536849Abstract: A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof.Type: GrantFiled: April 12, 2016Date of Patent: January 3, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Yajima, Hideki Harano, Katsuhiro Torii, Hironori Ochi
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Publication number: 20160322321Abstract: A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof.Type: ApplicationFiled: April 12, 2016Publication date: November 3, 2016Inventors: Akira YAJIMA, Hideki HARANO, Katsuhiro TORII, Hironori OCHI
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Publication number: 20160247772Abstract: A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Takaomi Nishi, Takehiko Saito, Katsuhiro Torii
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Patent number: 9362241Abstract: A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.Type: GrantFiled: August 18, 2015Date of Patent: June 7, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takaomi Nishi, Takehiko Saito, Katsuhiro Torii
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Publication number: 20160064343Abstract: A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.Type: ApplicationFiled: August 18, 2015Publication date: March 3, 2016Inventors: Takaomi Nishi, Takehiko Saito, Katsuhiro Torii
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Patent number: 8049263Abstract: A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved.Type: GrantFiled: April 6, 2009Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventor: Katsuhiro Torii
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Publication number: 20090189250Abstract: A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved.Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Inventor: Katsuhiro TORII
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Patent number: 7531419Abstract: A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved.Type: GrantFiled: May 12, 2006Date of Patent: May 12, 2009Assignee: Renesas Technology Corp.Inventor: Katsuhiro Torii
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Publication number: 20070052095Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using WPP by preventing a short-circuit failure between uppermost-level interconnects. In the present invention, a buffer layer is formed between an uppermost-level interconnect and redistribution interconnect. The uppermost-level interconnect is made of a copper film, while the buffer layer is made of an aluminum film. The redistribution interconnect is made of a film stack of a copper film and a nickel film. In such a semiconductor device, stress concentration occurs at a triple point when temperature cycling between low temperature and high temperature is performed. The stress concentration on the triple point is relaxed by the presence of the buffer layer, whereby the conduction of the stress to an interface just below the triple point can be suppressed. Peeling due to the stress at the interface can thus be prevented.Type: ApplicationFiled: September 5, 2006Publication date: March 8, 2007Inventors: Katsuhiro Torii, Shuji Matsuo
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Publication number: 20060255428Abstract: A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved.Type: ApplicationFiled: May 12, 2006Publication date: November 16, 2006Inventor: Katsuhiro Torii
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Patent number: 5085394Abstract: The invention provides a flat display supporting mechanism for a portable input/output device such as a computer or a word processor which employs a flat display having a large display area formed in a flat plate profile with a pivotable link attached between a back portion of the display and a device body. The device has a flat profile in a closed position. When the device is to be used, the display which is covering a keyboard is pivoted upwards together with the link. As the display reaches a vertical position the link having two pivot points around which the display is pivoted separates from the display and a lower portion of the flat display is moved away from the pivot point and towards the keyboard along a guide provided on the device body to a position where the flat display is positioned near the keyboard on the device body while a center portion of the display is supported by the link.Type: GrantFiled: January 24, 1990Date of Patent: February 4, 1992Assignee: Alps Electric Co., Ltd.Inventor: Katsuhiro Torii