Abstract: An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.

Abstract: A non-transitory computer-readable recording medium stores therein a program for causing a computer to execute a process for, in repeatedly training a given training model, repeatedly training the training model a given number of times by using a numerical value of a floating-point number, the numerical value being a parameter of the training model or training data of the training model, or any combination thereof; and, after the training by using the numerical value of the floating-point number, repeatedly training the training model by using a numerical value of a fixed-point number corresponding to a numerical value of the floating-point number obtained by the training.

Abstract: An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Abstract: An apparatus for data output control includes: an encryption executing circuit configured to receive first data from a processor with a control signal indicating whether the first data is to be encrypted, and encrypt the first data when the control signal indicates that the first data is to be encrypted; a selection circuit configured to output any of the encrypted first data and second data; and an output control unit configured to set a frequency of second timing to be smaller than a frequency of first timing, and transmit a signal to the selection circuit instructing that the second data be outputted at the second timing, in a case where the second data is received from the processor.

Abstract: A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.

Abstract: A processor includes; a first memory configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged; a second memory configured to store neighborhood matrix image data including pixel data of a neighborhood matrix; and a format converter that includes (a) a readout circuit configured to read out the image data from the first memory, (b) a padding arithmetic unit configured to receive the read-out image data, select pixel data of the received read-out image data and padding data inserted at periphery of the plurality of pixels in accordance with mask values of a padding mask, and generate the neighborhood matrix image data including the pixel data and the padding data, and (c) a writing circuit configured to write the neighborhood matrix image data to the second memory.

Abstract: A processor circuit includes: multiple processor cores; multiple individual memories; multiple shared memories; multiple memory control circuits; multiple selectors; and a control core; wherein when an address of the read request from the first processor associated with a specific memory control circuit is identical to the transfer source address, the specific memory control circuit controls the transfer data based on the read request to be transferred to the transfer destination address via a specific selector of the multiple selectors in which the transfer selection information is set, wherein, when the control core sets read selection information in each of the multiple selectors, read data is read by one of the first processor core and the first adjacent processor core from the associated shared memory via a specific selector of the multiple selectors in which the read selection information is set.

Abstract: An arithmetic processor includes a plurality of arithmetic circuits that individually execute an arithmetic operation for fixed point data; and at least one of first and second statistical information is acquired regarding a plurality of fixed point data that are results of arithmetic operation executed by the plurality of arithmetic circuits. The first statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from a least-significant-bit position to a highest-order bit position for each of the digits corresponding to the bit positions, and the second statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order-bit position for each of the digits corresponding to the bit positions.

Abstract: A simulation method performed by a computer for simulating a synchronous transfer between a plurality of cores, the method including steps of: performing processing for the synchronous transfer in each of the cores as a set of interrupt and interrupt wait processing; simulating a cycle for the synchronous transfer at a timing when reception of notifications of the interrupts from all the plurality of cores is completed; and synchronizing the cores by notifying the cores of interrupt responses to the interrupt wait processing executed in the cores at the timing.

Abstract: A simulation method performed by a computer for simulating operations by a plurality of cores based on resource access operation descriptions on the plurality of cores, the method includes steps of: extracting a resource access operation description on at least one core of the plurality of cores by executing simulation for the one core; and, under a condition where the one core and a second core among the plurality of cores have a specific relation in execution processing, generating a resource access operation description on the second core from the resource access operation description on the one core by reflecting an address difference between an address of a resource to which the one core accesses and an address of a resource to which the second core accesses.

Abstract: A login control method is executed by a computer. The login control method includes inputting a serial signal that corresponds to ON-operations and OFF-operations; measuring respective ON-times of the ON-operations and respective OFF-times of the OFF-operations of the input serial signal; referring to a storage unit, which stores average times for the respective ON-times, deviations for the respective ON-times, average times for the respective OFF-times, and deviations for the respective OFF-times, to determine whether the measured respective ON-times and the measured respective OFF-times are within permissible ranges; and permitting login in a case where the measured respective ON-times and the measured respective OFF-times are within the permissible ranges.

Abstract: An electronic apparatus includes a first DC-DC converter configured to generate a first direct-current power supply voltage based on an input direct-current voltage, a second DC-DC converter configured to generate a second direct-current power supply voltage based on the input direct-current voltage, a first circuit configured to operate with the first direct-current power supply voltage to perform a first process, a second circuit configured to operate with the second direct-current power supply voltage to perform a second process whose load is able to be reduced by the first process, and a control circuit configured to change, in response to the input direct-current voltage, a ratio between a volume of processing of the first process and a volume of processing of the second process.

Abstract: An electronic apparatus includes a first DC-DC converter configured to generate a first direct-current power supply voltage based on an input direct-current voltage, a second DC-DC converter configured to generate a second direct-current power supply voltage based on the input direct-current voltage, a first circuit configured to operate with the first direct-current power supply voltage to perform a first process, a second circuit configured to operate with the second direct-current power supply voltage to perform a second process whose load is able to be reduced by the first process, and a control circuit configured to change, in response to the input direct-current voltage, a ratio between a volume of processing of the first process and a volume of processing of the second process.

Abstract: A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.

Abstract: A signal processing circuit is configured by connecting a plurality of basic circuits connected in series, each of the basic circuits comprising an arithmetic circuit subjecting a first input signal and a second input signal to a signal processing; a first selection circuit outputting the first input signal or an output signal of the arithmetic circuit; and a second selection circuit outputting the second input signal or an output signal of the arithmetic circuit, so as to make it possible to change operations of the circuit as a whole by properly making a selection on which signal should be output with the aid of the first and second selection circuits, and to execute different signal processing on a single circuit depending on the selection.

Abstract: A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding stage circuit, an output enable signal generating unit generating an output enable signal outputting data stored in the data storing unit to the succeeding stage circuit by using one or more parameters for the protocol conversion which are externally fed and can take a different value each time interval externally specified, and an address specifying unit specifying an address for read of an output data for the data storing unit based on the output enable signal.

Abstract: A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.

Abstract: A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding stage circuit, an output enable signal generating unit generating an output enable signal outputting data stored in the data storing unit to the succeeding stage circuit by using one or more parameters for the protocol conversion which are externally fed and can take a different value each time interval externally specified, and an address specifying unit specifying an address for read of an output data for the data storing unit based on the output enable signal.

Abstract: A reconfigurable LSI which can actualize a plurality of functions by reconfiguration based on configuration information, comprises at least a plurality of arithmetic processing modules, has state information for indicating the transition of the function from a previous state to a next state, transition condition information for indicating the condition for transitioning from the previous state to the next state, and output information for switching the connection between the arithmetic processing module corresponding to the transition condition and the data network connected to the arithmetic processing module, and has a reconfiguration control circuit which transmits the output information corresponding to the next state to a selector for switching between the arithmetic processing module and the data network when the conditions for transition are received from the arithmetic processing module and matches the condition of the transition condition information.

Abstract: A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.