Abstract: A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

Abstract: A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

Abstract: A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

Abstract: The present invention provides a display control circuit comprising: a single transmission-control/priority-control circuit having a single output and two inputs, one of which receives a sequentially supplied screen data set, and the single transmission-control/priority-control circuit being capable of transmission-control and priority-control of the sequentially supplied screen data; and a single line buffer having a single input connected to the single output of the single transmission-control/priority-control circuit and two outputs, one of which is connected to other of the two inputs of the single transmission-control/priority-control circuit for sequentially supplying stored data into the other input of the single transmission-control/priority-control circuit every when new data are supplied from the single transmission-control/priority-control circuit so that the processes are continued sequentially until all data relating to all screens have been processed or the currently supplied data to be stored i