Patents by Inventor Katsuhito Sakurai

Katsuhito Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371908
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Patent number: 12057463
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: August 6, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Publication number: 20230097221
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Application
    Filed: December 1, 2022
    Publication date: March 30, 2023
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Patent number: 11552121
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 10, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Patent number: 11528445
    Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: December 13, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Katsuhito Sakurai, Yoshiaki Takada, Takahiro Shirai, Hideo Kobayashi, Kohichi Nakamura, Daisuke Yoshida, Fumihiro Inui
  • Patent number: 11503231
    Abstract: An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 15, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohei Matsumoto, Hirofumi Totsuka, Katsuhito Sakurai, Kohichi Nakamura
  • Patent number: 11425365
    Abstract: A photoelectric conversion device comprising: a first substrate that includes a pixel circuit including a photoelectric conversion element; a second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit; a connection part electrically connecting the first substrate and the second substrate; and an inspection circuit, wherein the inspection circuit is formed in one of the first and second substrates and is connected to a wire supplying a first potential and being provided in the one of the first and second substrates, and the inspection circuit is connected via the connection part to a wire supplying a second potential and being provided in the other of the first and second substrates.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 23, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryunosuke Ishii, Akira Oseto, Tatsunori Kato, Takanori Watanabe, Nobuaki Kakinuma, Hiroaki Kobayashi, Katsuhito Sakurai
  • Patent number: 11336844
    Abstract: An imaging device includes a plurality of pixels arranged to form a plurality of rows and a plurality of columns and each including a photoelectric converter, an accumulation time controller that controls accumulation time of the plurality of pixels, and an amplifier that amplifies a signal based on charge generated by the photoelectric converter. The plurality of pixels are divided into a plurality of pixel blocks each including at least two of the plurality of pixels, the accumulation time controller is configured to control the accumulation time individually for the plurality of pixel blocks, and the amplifier is configured to output, for one pixel block of the plurality of blocks, a plurality of signals which are amplified at different gains and correspond to accumulation time of a common frame.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 17, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hidetoshi Hayashi, Katsuhito Sakurai
  • Publication number: 20210368121
    Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Katsuhito Sakurai, Yoshiaki Takada, Takahiro Shirai, Hideo Kobayashi, Kohichi Nakamura, Daisuke Yoshida, Fumihiro Inui
  • Patent number: 11108986
    Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: August 31, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Katsuhito Sakurai, Yoshiaki Takada, Takahiro Shirai, Hideo Kobayashi, Kohichi Nakamura, Daisuke Yoshida, Fumihiro Inui
  • Publication number: 20210051282
    Abstract: An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: Kohei Matsumoto, Hirofumi Totsuka, Katsuhito Sakurai, Kohichi Nakamura
  • Patent number: 10904469
    Abstract: An imaging apparatus is provided and is configured in such a manner that a plurality of first pixels are connected to a first AD conversion unit, and a plurality of second pixels are connected to a second AD conversion unit whereby the imaging apparatus has a beneficial connection relationship between the pixels and the AD conversion units.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: January 26, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuuichirou Hatano, Katsuhito Sakurai, Atsushi Furubayashi
  • Publication number: 20200411582
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Patent number: 10855940
    Abstract: An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 1, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohei Matsumoto, Hirofumi Totsuka, Katsuhito Sakurai, Kohichi Nakamura
  • Patent number: 10811455
    Abstract: A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 20, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Kobayashi, Atsushi Furubayashi, Katsuhito Sakurai
  • Publication number: 20200244912
    Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Inventors: Katsuhito Sakurai, Yoshiaki Takada, Takahiro Shirai, Hideo Kobayashi, Kohichi Nakamura, Daisuke Yoshida, Fumihiro Inui
  • Patent number: 10708523
    Abstract: Provided is an imaging device configured to sequentially perform AD conversion for A signals of pixels of the first row, A signals of pixels of the second row, A+B signals of the pixels of the first row, and A+B signals of the pixels of the second row.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 7, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kei Ochiai, Katsuhito Sakurai, Atsushi Furubayashi
  • Publication number: 20200195916
    Abstract: A photoelectric conversion device comprising: a first substrate that includes a pixel circuit including a photoelectric conversion element; a second substrate having a signal processing circuit that drives the pixel circuit or processes a signal from the pixel circuit; a connection part electrically connecting the first substrate and the second substrate; and an inspection circuit, wherein the inspection circuit is formed in one of the first and second substrates and is connected to a wire supplying a first potential and being provided in the one of the first and second substrates, and the inspection circuit is connected via the connection part to a wire supplying a second potential and being provided in the other of the first and second substrates.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 18, 2020
    Inventors: Ryunosuke Ishii, Akira Oseto, Tatsunori Kato, Takanori Watanabe, Nobuaki Kakinuma, Hiroaki Kobayashi, Katsuhito Sakurai
  • Patent number: 10674106
    Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 2, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Katsuhito Sakurai, Yoshiaki Takada, Takahiro Shirai, Hideo Kobayashi, Kohichi Nakamura, Daisuke Yoshida, Fumihiro Inui
  • Publication number: 20200068147
    Abstract: An imaging device includes a plurality of pixels arranged to form a plurality of rows and a plurality of columns and each including a photoelectric converter, an accumulation time controller that controls accumulation time of the plurality of pixels, and an amplifier that amp1ifies a signal based on charge generated by the photoelectric converter. The plurality of pixels are divided into a plurality of pixel blocks each including at least two of the plurality of pixels, the accumulation time controller is configured to control the accumulation time individually for the plurality of pixel blocks, and the amplifier is configured to output, for one pixel block of the plurality of blocks, a plurality of signals which are amp1ified at different gains and correspond to accumulation time of a common frame.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 27, 2020
    Inventors: Hidetoshi Hayashi, Katsuhito Sakurai