Abstract: A virtual computer system of a multi-processor arrangement reduces the overhead of XPTLB processing. The processing of a PTLB (translation look-aside buffer processing) is controlled using IP dispatch information about virtual computers that is stored a hardware share area (HSA). A control unit (CU) has a group of bit-map BIM (broadcast IP mask) latches which correspond to the configured IP's and in which the IP dispatch information is set upon purging of a translation look-aside buffer. Through AND gate logic provided in the CU, whether or not an IP is to receive a PTLB request is determined on the basis of the information set in the BIM masks. Specifically, the AND gates compute the logical AND of each of the BIM masks with the control line of a XPTLB REQ from an IP being dispatched by a particular virtual computer.