Abstract: An automatic switching mechanism is controlled by a probe card independent from a tester without limitation of the number of control signals from the tester. A probe card and an inspection apparatus include probes to be brought into contact with electrodes of inspection targets and a power supply channel electrically connecting the probes to a tester. The automatic switching mechanism divides each of the power supply channels into a plurality of power supply wiring portions, which are respectively connected to the probes; and shuts off the power supply wiring responsive to electrical fluctuation such as overcurrent. An electrical fluctuation detection mechanism detects an electrical fluctuation due to a defective product among the inspection targets. A control mechanism, responsive to detection of an electrical fluctuation, shuts off the power supply wiring portion if the electrical fluctuation is caused by the automatic switching mechanism.

Abstract: An embodiment of an electrical connecting apparatus comprises a probe base plate and a plurality of contacts provided with tips to be pressed against electrodes of a device under test and arranged on the underside of the probe base plate. The distance dimensions from an imaginary plane parallel to the probe base plate to the tips of the contacts are made the greater toward the center of the probe base plate.

Abstract: An automatic switching mechanism is controlled by a probe card independent from a tester without limitation of the number of control signals from the tester. A probe card and an inspection apparatus include probes to be brought into contact with electrodes of inspection targets and a power supply channel electrically connecting the probes to a tester. The automatic switching mechanism divides each of the power supply channels into a plurality of power supply wiring portions, which are respectively connected to the probes; and shuts off the power supply wiring responsive to electrical fluctuation such as overcurrent. An electrical fluctuation detection mechanism detects an electrical fluctuation due to a defective product among the inspection targets. A control mechanism, responsive to detection of an electrical fluctuation, shuts off the power supply wiring portion if the electrical fluctuation is caused by the automatic switching mechanism.

Abstract: The present invention aims to provide such a joint structure of a wound coil 1 and an IC chip 2 for a noncontact RFID device that is able to yield electrically and mechanically excellent connection, employing the wound coil 1, which is made by winding copper electric wire, with small variance of the electric resistance as an antenna coil for the noncontact RFID device, also by making use of such IC chips that their joint terminals 3 are covered with such metallization of the gold outermost layer 3a that is not liable to degradation during storage; and aims to provide such a method of joining the wound coil 1 and the IC chip 2 for the noncontact RFID device that is able to make said joint structure with ease and certainty, through selecting a direct joining process low in production cost as the joining method of the two, also through improving the process.

Abstract: An embodiment of an electrical connecting apparatus comprises a probe base plate and a plurality of contacts provided with tips to be pressed against electrodes of a device under test and arranged on the underside of the probe base plate. The distance dimensions from an imaginary plane parallel to the probe base plate to the tips of the contacts are made the greater toward the center of the probe base plate.

Abstract: A semiconductor memory comprises: at least two word lines; at least two bit lines which are arranged in a manner crossing the word lines; a reference potential generating circuit for generating a predetermined reference potential; reference potential transfering circuits for transfering the reference potential to the bit lines; at least two memory cells arranged at intersections of the word lines and the bit lines; a sense amplifier for amplifying potential difference between the bit lines; a test mode determination circuit for detecting signal information for starting a predetermined test; and a sense time control circuit taking an output signal from the test mode determination circuit as its input so as to control an operation delay time of the sense amplifier and the word lines.

Abstract: The dynamic memory of the present invention allows refresh operations with low power consumption and with easy control. The dynamic memory includes a detection circuit which detects a decrease in the power voltage source and a control circuit to automatically refresh a memory cell in response to the detected signal.

Abstract: A semiconductor memory device is used for storing data bits in memory cells thereof, and the data bits are read out from the memory cells in the form of small differences in voltage level on bit line pairs coupled to the memory cells, wherein gate transistors are inserted between each of the bit line pairs and a pair of sense nodes, and in which the bit line pair and the sense node pair are respectively associated with first and second sense amplifier circuits for rapidly increasing the small difference in voltage level, because the electric charges accumulated in the bit line pair are shared by the first and second sense amplifier circuits.

Abstract: A signal input circuit of a type in which an input signal voltage is compared with a reference voltage is disclosed. A first gate is connected in series with a first input transistor between a first terminal of an input amplifier comprising a flip-flop circuit and a reference terminal. A second gate is connected in series with a second input transistor between a second terminal of the input amplifier and the reference terminal. The first and second gates are controlled by potentials at third and fourth terminals of the input amplifier. The input terminals of an output amplifier are coupled to the first and second terminals of the input amplifier to provide output signals.

Abstract: An input buffer circuit includes a flipflop circuit and receives an input voltage signal and a reference voltage to amplify a difference between the input voltage signal and the reference voltage in response to an activation signal. The input buffer circuit comprises first and second transistors having their sources commonly connected to a first node and their drains coupled to a pair of inputs of the flipflop circuit, respectively. A gate of the first transistor is connected to receive the input voltage signal and a gate of the second transistor is connected to receive the reference voltage. A capacitor is connected at its one end to the first node and at its other end to a second node.

Abstract: A latch circuit includes a current source, and a flip-flop amplifier circuit having a pair of first and second input terminals for comparing a reference voltage and an external input voltage with each other and amplifying the voltage difference therebetween in response to inputting of an activating signal. A first transistor has a source terminal, a drain terminal connected to the first input terminal of the flip-flop amplification circuit, and a gate terminal receptive of the external input voltage. A second transistor has a source terminal connected to the source terminal of the first transistor, a drain terminal connected to the second input terminal of the flip-flop amplification circuit, and a gate terminal receptive of the reference voltage.

Abstract: A semiconductor integrated circuit having a voltage generator circuit for generating an internal power voltage lower than an externally supplied power voltage, a control circuit for generating at least one control signal and a functional circuit operating with the internal power voltage and controlled by the control signal is disclosed and featured in that the control circuit includes a first circuit operating with the externally supplied power voltage and generating a first signal with a predetermined timing relationship with respect to an input control signal thereto and a second circuit operating with the internal voltage and generating a second signal in response to the first signal, as the control signal for the functional circuit.

Abstract: A signal input circuit of a type in which an input signal voltage is compared with a reference voltage is disclosed. The input signal voltage is supplied to a first transistor coupled between a first input terminal of a flip-flop circuit and a reference terminal, and the reference voltage is supplied to a second transistor coupled between a second input terminal of the flip-flop circuit and the reference terminal. A first gate is inserted in series to the first transistor between the first input terminal and the reference terminal, and a second gate is inserted in series to the second transistor between the second input terminal and the reference terminal. The first and second gates are controlled by potentials at the second and first output terminals, respectively.

Abstract: A memory circuit which can perform a write operation at a high-speed is disclosed. The memory circuit has an input circuit receiving an external read-write signal which has a direct connection to a terminal receiving a chip control signal such as a column address strobe signal and is adapted to be directly controlled by the chip control signal itself.

Abstract: A reference voltage generator circuit which can operate stably irrespective of variations in a power supply voltage and in threshold voltage of transistors employed is disclosed.