Abstract: Process for producing a high-density printed wiring board, comprising: providing an ultrathin-copper-foil-clad board having a hole and outermost copper foil thickness of 5 ?m or less, plating the surface by electroless copper plating to form a layer of 0.1 to 1 ?m thickness, forming an electrolytic copper plating layer of 0.5 to 3 ?m thickness using the electroless copper plating layer as electrode, forming a plating resist layer on a portion of the copper plating layer, forming a pattern copper plating layer of 6 to 30 ?m thickness on the copper surface in where the plating resist layer is not formed, by electrolytic plating, removing the plating resist layer, and etching the entire surface to remove the thin electrolytic copper layer, the electroless copper layer and ultrathin copper foil layer at least where the pattern copper plating layer is not formed.

Abstract: A process for the production of a high-density printed wiring board, comprising the steps of

Abstract: Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased.

Abstract: A printed wiring board for a ball grid array type semiconductor plastic package which has excellent heat diffusibility and causes no popcorn phenomenon, and a metal-plate-inserted printed wiring board having wire bonding pads formed at two levels, for use in the ball grid array type semiconductor plastic package.

Abstract: Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased.

Abstract: Printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package. The distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The board has at least two blind via holes in one solder-balls-fixing pad.

Abstract: A substrate 1 of a insulating resin material is provided with a semiconductor chip 2 in the center of the substrate 1 and a lot of fine studs are filled in the substrate 1 around the chip 2. A bonding pad 13 and a land 14 are formed on both end planes of each stud 12 by silver plating. The length of the stud 12 is determined so that the plane of the land 14 and the back side plane of the substrate are approximately co-planar, but it may be longer. The substrate 1 including the studs 12 having the bonding pad 12 and the land 14 is defined as an interposer 15.

Abstract: A substrate 1 of a insulating resin material is provided with a semiconductor chip 2 in the center of the substrate 1 and a lot of fine studs are filled in the substrate 1 around the chip 2. A bonding pad 13 and a land 14 are formed on both end planes of each stud 12 by silver plating. The length of the stud 12 is determined so that the plane of the land 14 and the back side plane of the substrate are approximately co-planar, but it may be longer. The substrate 1 including the studs 12 having the bonding pad 12 and the land 14 is defined as an interposer 15.

Abstract: A resin encapsulated pin grid array includes an IC chip mounted on a resin substrate having a plurality of contact pins on its lower surface and resin-encapsulated by injection molding. A metal heat radiating member is integrally formed on the upper surface of the encapsulating resin when the encapsulating resin is injection-molded.

Abstract: A resin encapsulated pin grid array includes an IC chip mounted on a resin substrate having a plurality of contact pins on its lower surface and resin-encapsulated by injection molding. A metal heat radiating member is integrally formed on the upper surface of the encapsulating resin when the encapsulating resin is injection-molded.

Abstract: A method of making a resin encapsulated pin grid array includes an IC chip mounted on a resin substrate having a plurality of contact pins on its lower surface and resin-encapsulated by injection molding. A metal heat radiating member is integrally formed on the upper surface of the encapsulating resin when the encapsulating resin is injection-molded.

Abstract: A method of making a resin encapsulated pin grid array which includes an IC chip mounted on a resin substrate having a plurality of contact pins on its lower surface and resin-encapsulated by injection molding. A metal heat radiating member is integrally formed on the upper surface of the encapsulating resin when the encapsulating resin is injection-molded.

Abstract: A resin encapsulating method includes the steps of mounting a plate having a gate groove on a substrate to form a side gate, connected to the side surface of a cavity, between the plate and one of the upper and lower half molds, and filling a resin in the cavity.