Patents by Inventor Katsuji Matsumoto
Katsuji Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240322028Abstract: Provided is a semiconductor device (1) having high heat dissipation and high operation reliability. This semiconductor device includes: a semiconductor substrate (10); a first semiconductor layer (20) that is provided on the semiconductor substrate, has a first aperture (20K), and has a first thermal conductivity; a transistor (Tr) provided on the first semiconductor layer; and a heat dissipation unit (40) that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.Type: ApplicationFiled: March 18, 2022Publication date: September 26, 2024Inventors: KATSUJI MATSUMOTO, NAOKI KAKOIYAMA
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Patent number: 12068407Abstract: A semiconductor device includes: a semiconductor substrate; a channel layer on the semiconductor substrate; a barrier layer on the channel layer; a gate electrode on the barrier layer via a gate insulating film; a source electrode and a drain electrode on the channel layer with the gate electrode interposed therebetween; a substrate opening that penetrates the channel layer and exposes the semiconductor substrate; an insulating film provided from upper parts of the gate electrode, the source electrode, and the drain electrode to an inner side of the substrate opening; and a wiring line layer on the insulating film, and electrically coupled to one of the gate electrode, the source electrode, and the drain electrode via an opening on the insulating film, in which at least a portion of the substrate opening is in an activation region in which the gate electrode, the source electrode, and the drain electrode are provided.Type: GrantFiled: September 20, 2019Date of Patent: August 20, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Katsuji Matsumoto, Masashi Yanagita
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Publication number: 20210359120Abstract: A semiconductor device includes: a semiconductor substrate; a channel layer on the semiconductor substrate; a barrier layer on the channel layer; a gate electrode on the barrier layer via a gate insulating film; a source electrode and a drain electrode on the channel layer with the gate electrode interposed therebetween; a substrate opening that penetrates the channel layer and exposes the semiconductor substrate; an insulating film provided from upper parts of the gate electrode, the source electrode, and the drain electrode to an inner side of the substrate opening; and a wiring line layer on the insulating film, and electrically coupled to one of the gate electrode, the source electrode, and the drain electrode via an opening on the insulating film, in which at least a portion of the substrate opening is in an activation region in which the gate electrode, the source electrode, and the drain electrode are provided.Type: ApplicationFiled: September 20, 2019Publication date: November 18, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Katsuji MATSUMOTO, Masashi YANAGITA
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Publication number: 20200233098Abstract: The present technology relates to a light-receiving device that makes it possible to simplify readout from a plurality of pixels and a process after the readout, without deteriorating light receiving sensitivity and characteristics in resolution. A plurality of unit elements is disposed above a substrate, each of the unit elements including a plurality of pixels disposed in m number of rows and n number of columns, and a readout section that sequentially reads out signals from a plurality of pixels disposed in a column direction among the plurality of pixels. The number of readout sections is at least the same as the number of columns. The readout section includes a QV amplifier. The present technology is applicable to the light-receiving device that detects radiation.Type: ApplicationFiled: February 8, 2018Publication date: July 23, 2020Inventors: KATSUJI MATSUMOTO, TAKAHIRO IGARASHI, TAKAHIRO SONODA
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Publication number: 20190103501Abstract: A light-receiving device of an embodiment of the present disclosure includes, on a first principal surface of a semiconductor layer, a pixel region that includes a plurality of light-receiving pixels each receiving light incident from side of a second principal surface of the semiconductor layer. The light-receiving device further includes, throughout a gap between the second principal surface and the pixel region, a low-impurity region having a relatively lower impurity concentration than the pixel region. The light-receiving pixels each include one or a plurality of photoelectric current extraction regions each including, on the first principal surface, an anode region and a cathode region, and a circuit region that is electrically coupled to each of the cathode regions and is electrically separated from the impurity region.Type: ApplicationFiled: February 15, 2017Publication date: April 4, 2019Applicant: SONY CORPORATIONInventors: Takahiro IGARASHI, Takahiro SONODA, Atsushi SUZUKI, Shinya YAMAKAWA, Hiroshi YUMOTO, Izuho HATADA, Takeshi KODAMA, Kiwamu ADACHI, Katsuji MATSUMOTO
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Publication number: 20190049599Abstract: An imaging apparatus includes: a substrate; and a plurality of device sections each including a photoelectric converter and disposed on the substrate to be spaced from one another and to collectively form a concave shape.Type: ApplicationFiled: January 17, 2017Publication date: February 14, 2019Applicant: SONY CORPORATIONInventors: Katsuji MATSUMOTO, Shusaku YANAGAWA, Takahiro IGARASHI, Hiroshi ICHIKI
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Patent number: 10134662Abstract: A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes; (2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.Type: GrantFiled: September 8, 2015Date of Patent: November 20, 2018Assignee: Sony CorporationInventors: Kiwamu Adachi, Katsuji Matsumoto, Takeshi Kodama, Shuichi Oka, Hiizu Ootorii, Kazunari Saitou, Kei Satou
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Patent number: 9929199Abstract: There is provided a radiation detector including: a plurality of photoelectric conversion devices, each photoelectric conversion device formed at least partially within an embedding layer and having a light receiving surface situated at least partially outside of the embedding layer, and a plurality of scintillator crystals, at least a first scintillator crystal of the plurality of scintillator crystals in contact with at least one light receiving surface at a proximal end, wherein a cross-section of the first scintillator crystal at the proximal end is smaller than a cross-section of the first scintillator crystal at a distal end.Type: GrantFiled: August 21, 2014Date of Patent: March 27, 2018Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takahiro Igarashi, Izuho Hatada, Takeshi Kodama, Kiwamu Adachi, Shuichi Oka, Shun Mitarai, Hiizu Ootorii, Shusaku Yanagawa, Katsuji Matsumoto
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Publication number: 20170287823Abstract: A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes; (2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.Type: ApplicationFiled: September 8, 2015Publication date: October 5, 2017Applicant: Sony CorporationInventors: Kiwamu Adachi, Katsuji Matsumoto, Takeshi Kodama, Shuichi Oka, Hiizu Ootorii, Kazunari Saitou, Kei Satou
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Patent number: 9391036Abstract: A semiconductor device includes a first semiconductor electronic component which includes a pad electrode, a solder bump, and a metal layer between a pad and solder that is configured to have an underlying metal layer formed between the pad electrode and the solder bump and connected to the pad electrode, and a main metal layer formed on the underlying metal layer, and in which the main metal layer has an eave portion at an outer edge portion thereof.Type: GrantFiled: June 3, 2014Date of Patent: July 12, 2016Assignee: SONY CORPORATIONInventors: Katsuji Matsumoto, Hiizu Ootorii
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Publication number: 20160163754Abstract: There is provided a radiation detector including: a plurality of photoelectric conversion devices, each photoelectric conversion device formed at least partially within an embedding layer and having a light receiving surface situated at least partially outside of the embedding layer, and a plurality of scintillator crystals, at least a first scintillator crystal of the plurality of scintillator crystals in contact with at least one light receiving surface at a proximal end, wherein a cross-section of the first scintillator crystal at the proximal end is smaller than a cross-section of the first scintillator crystal at a distal end.Type: ApplicationFiled: August 21, 2014Publication date: June 9, 2016Inventors: Takahiro Igarashi, Izuho Hatada, Takeshi Kodama, Kiwamu Adachi, Shuichi Oka, Shun Mitarai, Hiizu Ootoril, Shusaku Yanagawa, Katsuji Matsumoto
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Publication number: 20140361431Abstract: A semiconductor device includes a first semiconductor electronic component which includes a pad electrode, a solder bump, and a metal layer between a pad and solder that is configured to have an underlying metal layer formed between the pad electrode and the solder bump and connected to the pad electrode, and a main metal layer formed on the underlying metal layer, and in which the main metal layer has an eave portion at an outer edge portion thereof.Type: ApplicationFiled: June 3, 2014Publication date: December 11, 2014Applicant: Sony CorporationInventors: Katsuji Matsumoto, Hiizu Ootorii
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Patent number: 8482107Abstract: A device that comprises a plurality of circuit elements on a substrate; a shielding element between at least two of the plurality of circuit elements; and a bonding element that electrically connects the shielding element to a grounding circuit of a semiconductor chip that is on the substrate.Type: GrantFiled: November 8, 2010Date of Patent: July 9, 2013Assignee: Sony CorporationInventors: Shinji Rokuhara, Shuichi Oka, Katsuji Matsumoto, Shusaku Yanagawa
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Patent number: 8338912Abstract: Disclosed herein is an inductor module including a substrate functioning as a printed wiring board or an interposer; an IC mounting part formed on a surface of the substrate; an inductor which is formed in the substrate at such a position as to overlap with the IC mounting part on a plan-view basis and which is connected to an IC mounted on the IC mounting part; and a magnetic body including a magnetic material selected from among a NiZn ferrite, a NiZnCu ferrite and a Ba ferrite, the magnetic body being disposed intermediately between the IC mounting part and the inductor.Type: GrantFiled: June 10, 2009Date of Patent: December 25, 2012Assignee: Sony CorporationInventors: Shuichi Oka, Katsuji Matsumoto, Shusaku Yanagawa
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Publication number: 20120241204Abstract: A thin film capacitor includes: two electrode layers; a dielectric film interposed between the two electrode layers; an opening that pierces through, together with the dielectric film, in the thickness direction, any one of the two electrode layers or a conductive layer in the same level adjacent to one of the two electrode layers; and a reinforcing member that couples, in the opening, a side surface of the dielectric film to a side surface of the one electrode layer or the conductive layer.Type: ApplicationFiled: March 22, 2012Publication date: September 27, 2012Applicant: SONY CORPORATIONInventors: Katsuji Matsumoto, Shusaku Yanagawa, Satoshi Horiuchi, Shuichi Oka
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Patent number: 8254144Abstract: A circuit board laminated module includes: a first circuit board having a multi-layer structure in which ground layers are provided in a plurality of layers; a second circuit board mounted on the first circuit board; and a semiconductor chip mounted on the second circuit board, wherein in the first circuit board, a noise guiding through via which guides an electromagnetic noise generated in the semiconductor chip to a lower layer side is provided on a side different from a circuit portion or a circuit element desired to be protected against influence of the electromagnetic noise in a surrounding direction of an occurrence place of the electromagnetic noise.Type: GrantFiled: December 16, 2010Date of Patent: August 28, 2012Assignee: Sony CorporationInventors: Katsuji Matsumoto, Shusaku Yanagawa, Shuichi Oka, Shinji Rokuhara
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Publication number: 20110156224Abstract: A device that comprises a plurality of circuit elements on a substrate; a shielding element between at least two of the plurality of circuit elements; and a bonding element that electrically connects the shielding element to a grounding circuit of a semiconductor chip that is on the substrate.Type: ApplicationFiled: November 8, 2010Publication date: June 30, 2011Applicant: Sony CorporationInventors: Shinji Rokuhara, Shuichi Oka, Katsuji Matsumoto, Shusaku Yanagawa
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Publication number: 20110157857Abstract: A circuit board laminated module includes: a first circuit board having a multi-layer structure in which ground layers are provided in a plurality of layers; a second circuit board mounted on the first circuit board; and a semiconductor chip mounted on the second circuit board, wherein in the first circuit board, a noise guiding through via which guides an electromagnetic noise generated in the semiconductor chip to a lower layer side is provided on a side different from a circuit portion or a circuit element desired to be protected against influence of the electromagnetic noise in a surrounding direction of an occurrence place of the electromagnetic noise.Type: ApplicationFiled: December 16, 2010Publication date: June 30, 2011Applicant: Sony CorporationInventors: Katsuji Matsumoto, Shusaku Yanagawa, Shuichi Oka, Shinji Rokuhara
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Publication number: 20100148905Abstract: Disclosed herein is an inductor module including a coil section provided with an input terminal and an output terminal. At least one of the input terminal and the output terminal is composed of a plurality of terminals. The input terminal and the output terminal are connected at different positions. The connection of the plurality of terminals constituting the input terminal or the output terminal is switched so as to change the combination of the input terminal and the output terminal, obtaining different inductance values.Type: ApplicationFiled: November 24, 2009Publication date: June 17, 2010Applicant: Sony CorporationInventor: Katsuji Matsumoto
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Publication number: 20090309185Abstract: Disclosed herein is an inductor module including a substrate functioning as a printed wiring board or an interposer; an IC mounting part formed on a surface of the substrate; an inductor which is formed in the substrate at such a position as to overlap with the IC mounting part on a plan-view basis and which is connected to an IC mounted on the IC mounting part; and a magnetic body including a magnetic material selected from among a NiZn ferrite, a NiZnCu ferrite and a Ba ferrite, the magnetic body being disposed intermediately between the IC mounting part and the inductor.Type: ApplicationFiled: June 10, 2009Publication date: December 17, 2009Applicant: Sony CorporationInventors: Shuichi OKA, Katsuji MATSUMOTO, Shusaku YANAGAWA