Patents by Inventor Katsuji Matsuta

Katsuji Matsuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7911311
    Abstract: An electronic component is configured to include a laminate disposed between first and second magnetic substrates. The laminate is formed by laminating resin insulating layers, a coil pattern, and a lead pattern. The coil pattern is connected to external electrodes disposed on end surfaces of the laminate by using internal electrodes. The electronic component further includes expansion relaxation portions disposed in the inside of the resin insulating layers and located in the vicinity of connection regions of the internal electrodes and the external electrodes. The expansion relaxation portions are formed by using a magnetic powder resin in which a ferrite powder and a resin material are mixed.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 22, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Katsuji Matsuta, Masahiko Kawaguchi
  • Patent number: 7843701
    Abstract: An electronic component and an electronic-component production method in which the magnitude of a stray capacitance produced between adjacent outer electrodes is controllable. The electronic component includes a chip body and first to fourth outer electrodes. In the chip body, first and second coil block are sandwiched between magnetic substrates. Dielectric layers are interposed between the outer electrodes and the chip body such as to be away from exposed portions of coil patterns in the coil blocks. The dielectric layers have a width larger than a width of the outer electrodes, and a dielectric constant of the dielectric layers is set to be lower than the dielectric constant of the magnetic substrates.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: November 30, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuhide Kudo, Minoru Matsunaga, Katsuji Matsuta
  • Publication number: 20100052838
    Abstract: An electronic component is configured to include a laminate disposed between first and second magnetic substrates. The laminate is formed by laminating resin insulating layers, a coil pattern, and a lead pattern. The coil pattern is connected to external electrodes disposed on end surfaces of the laminate by using internal electrodes. The electronic component further includes expansion relaxation portions disposed in the inside of the resin insulating layers and located in the vicinity of connection regions of the internal electrodes and the external electrodes. The expansion relaxation portions are formed by using a magnetic powder resin in which a ferrite powder and a resin material are mixed.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 4, 2010
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsuji Matsuta, Masahiko Kawaguchi
  • Patent number: 7439842
    Abstract: A laminated balun transformer that achieves improved balance characteristics and prevents the occurrence of parasitic inductance has an impedance transformation ratio of one to four and outputs balanced signals generated from an unbalanced signal. The laminated balun transformer includes a magnetic substrate, a laminated body, and external electrodes. The laminated body includes a first transformer, a second transformer, and a non-magnetic body which completely covers the first and second transformers from the outside. The first and second transformers are arranged side by side in a direction substantially parallel to the magnetic substrate. A primary coil of the first transformer and a secondary coil of the second transformer are configured to be 180-degree rotationally symmetric with respect to a center line, while a secondary coil and a primary coil are also configured to be 180-degree rotationally symmetric with respect to the center line L.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: October 21, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuhiro Fujiki, Katsuji Matsuta, Kosuke Ishida
  • Publication number: 20080130258
    Abstract: An electronic component and an electronic-component production method in which the magnitude of a stray capacitance produced between adjacent outer electrodes is controllable. The electronic component includes a chip body and first to fourth outer electrodes. In the chip body, first and second coil block are sandwiched between magnetic substrates. Dielectric layers are interposed between the outer electrodes and the chip body such as to be away from exposed portions of coil patterns in the coil blocks. The dielectric layers have a width larger than a width of the outer electrodes, and a dielectric constant of the dielectric layers is set to be lower than the dielectric constant of the magnetic substrates.
    Type: Application
    Filed: July 3, 2007
    Publication date: June 5, 2008
    Inventors: Kazuhide Kudo, Minoru Matsunaga, Katsuji Matsuta
  • Patent number: 7369028
    Abstract: A coil component includes a first coil block and a second coil block that are sandwiched between magnetic substrates so as to form a chip body, and external electrodes that are attached to the chip body. The first coil block includes a coil body and an insulating body. The coil body includes an outer coil portion and an inner coil portion. The outer coil portion includes a first pattern group and a second pattern group, which are connected helically vertically in an alternating fashion. The inner coil portion includes a first spiral pattern and a second spiral pattern, which are connected to each other in series. In other words, low stray capacitance is achieved by the outer coil portion, while high inductance is achieved by the inner coil portion.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: May 6, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Minoru Matsunaga, Masahiko Kawaguchi, Katsuji Matsuta, Kazuhide Kudo, Kenichi Ito
  • Publication number: 20080062727
    Abstract: A laminated balun transformer that achieves improved balance characteristics and prevents the occurrence of parasitic inductance has an impedance transformation ratio of one to four and outputs balanced signals generated from an unbalanced signal. The laminated balun transformer includes a magnetic substrate, a laminated body, and external electrodes. The laminated body includes a first transformer, a second transformer, and a non-magnetic body which completely covers the first and second transformers from the outside. The first and second transformers are arranged side by side in a direction substantially parallel to the magnetic substrate. A primary coil of the first transformer and a secondary coil of the second transformer are configured to be 180-degree rotationally symmetric with respect to a center line, while a secondary coil and a primary coil are also configured to be 180-degree rotationally symmetric with respect to the center line L.
    Type: Application
    Filed: November 14, 2007
    Publication date: March 13, 2008
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasuhiro Fujiki, Katsuji Matsuta, Kosuke Ishida
  • Publication number: 20070205856
    Abstract: A coil component includes a first coil block and a second coil block that are sandwiched between magnetic substrates so as to form a chip body, and external electrodes that are attached to the chip body. The first coil block includes a coil body and an insulating body. The coil body includes an outer coil portion and an inner coil portion. The outer coil portion includes a first pattern group and a second pattern group, which are connected helically vertically in an alternating fashion. The inner coil portion includes a first spiral pattern and a second spiral pattern, which are connected to each other in series. In other words, low stray capacitance is achieved by the outer coil portion, while high inductance is achieved by the inner coil portion.
    Type: Application
    Filed: May 2, 2007
    Publication date: September 6, 2007
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Minoru MATSUNAGA, Masahiko KAWAGUCHI, Katsuji MATSUTA, Kazuhide KUDO, Kenichi ITO
  • Patent number: 6998951
    Abstract: A common mode choke coil array of a two-element type includes two common mode choke coil elements including at least two spiral coils and arranged side by side in a laminate body (chip member) in plan view. The spiral coils are configured so that the number of turns of the coils on the sides thereof where the coils are adjacent to each other is smaller than the number of turns of the coils on the sides thereof where the coils are distant from each other. The spiral directions of the coils arranged side by side are opposite to each other.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: February 14, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Itou, Katsuji Matsuta, Masahiko Kawaguchi
  • Patent number: 6710694
    Abstract: A coil device includes a first magnetic substrate, a laminated body disposed on the first magnetic substrate and having insulating layers, coil patterns, and at least one through-hole, a magnetic layer covering the upper surface of the laminated body, an adhesive layer disposed on the magnetic layer, and a second magnetic substrate disposed on the adhesive layer and bonded to the magnetic layer via the adhesive layer. The insulating layers defining an insulator and the coil patterns for forming a coil are alternately stacked so that the coil patterns are arranged in the insulator, the through-hole is located at an area where the coils are not located and extends from the upper surface of the laminated body to the first magnetic substrate. The magnetic layer has at least one portion extending through the through-hole to contact the first magnetic substrate. The adhesive layer is nonmagnetic, and the laminated body is sandwiched between the first and second substrates.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: March 23, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Katsuji Matsuta, Kenichi Ito, Masahiko Kawaguchi
  • Publication number: 20030137384
    Abstract: A common mode choke coil array of a two-element type includes two common mode choke coil elements including at least two spiral coils and arranged side by side in a laminate body (chip member) in plan view. The spiral coils are configured so that the number of turns of the coils on the sides thereof where the coils are adjacent to each other is smaller than the number of turns of the coils on the sides thereof where the coils are distant from each other. The spiral directions of the coils arranged side by side are opposite to each other.
    Type: Application
    Filed: January 2, 2003
    Publication date: July 24, 2003
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Itou, Katsuji Matsuta, Masahiko Kawaguchi
  • Publication number: 20030076211
    Abstract: A coil device includes a first magnetic substrate, a laminated body disposed on the first magnetic substrate and having insulating layers, coil patterns, and at least one through-hole, a magnetic layer covering the upper surface of the laminated body, an adhesive layer disposed on the magnetic layer, and a second magnetic substrate disposed on the adhesive layer and bonded to the magnetic layer via the adhesive layer. The insulating layers defining an insulator and the coil patterns for forming a coil are alternately stacked so that the coil patterns are arranged in the insulator, the through-hole is located at an area where the coils are not located and extends from the upper surface of the laminated body to the first magnetic substrate. The magnetic layer has at least one portion extending through the through-hole to contact the first magnetic substrate. The adhesive layer is nonmagnetic, and the laminated body is sandwiched between the first and second substrates.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 24, 2003
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Katsuji Matsuta, Kenichi Ito, Masahiko Kawaguchi
  • Patent number: 6389680
    Abstract: A method of manufacturing an electronic component secures sufficient area such that an element of the electronic component can be formed on the surface of a mother substrate while preventing debris from an insulating film from remaining on the element. According the method, individual elements are cut out from the mother substrate by cutting the mother substrate along cut lines A and B by using a dicing process wherein a protecting film is not located only at portions of the surface of the mother substrate where cut lines A and B intersect with each other and the surface of the mother substrate is exposed only at the intersection portions.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: May 21, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Katsuji Matsuta, Masahiko Kawaguchi
  • Patent number: 6276995
    Abstract: A method of manufacturing an electronic component provides a wide area which can be used for forming elements on the surface of a mother substrate and effectively produces an electronic component having excellent performance characteristics. At least a portion of the mother substrate is cut by using a blade having a shape in which a portion thereof butted against the boundary (shoulder) between the electrode arrangement surface and the cut end surface of the mother substrate or a portion which becomes the boundary (shoulder) is inclined at a predetermined angle to form an inclined surface at the boundary (shoulder) or the portion which becomes the boundary (shoulder) so as to expose a part of an electrode at the inclined surface.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: August 21, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Katsuji Matsuta, Kazuyoshi Uchiyama, Masahiko Kawaguchi, Katsuhiro Misaki, Naoki Iida
  • Patent number: 6114938
    Abstract: A variable inductor device has at least two coils. The at least two coils are disposed on an insulating substrate with an inductance adjusting element located therebetween. The inductance adjusting element is electrically connected at one end to a tap center electrode. The at least two coils are electrically connected to each other via the inductance adjusting element. The inductance adjusting element is grooved and horizontal paths of the inductance adjusting element are sequentially disconnected one by one by, for example, a laser beam. The inductances are thus varied. It is therefore possible to provide a variable inductor device in which the area required for mounting the device on a printed circuit board is decreased and the inductances are stably adjusted while keeping the inductances balanced.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: September 5, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Naoki Iida, Kazuyoshi Uchiyama, Katsuji Matsuta, Masahiko Kawaguchi
  • Patent number: 6035528
    Abstract: A method of manufacturing an electronic component includes forming a slit in a connecting electrode located on the surface of a mother substrate such that the slit extends in a direction intersecting a cutting line, and cutting the mother substrate along the cutting line while cutting the connecting electrode having the slit. The connecting electrode is thereby reliably exposed on two opposing cut surfaces, and the reliability of external connection of the electronic component is improved.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: March 14, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshiya Sasaki, Kazuyoshi Uchiyama, Masahiko Kawaguchi, Katsuhiro Misaki, Katsuji Matsuta
  • Patent number: 5955931
    Abstract: There is provided a chip type filter which can be made compact, allows the matching of input/output impedance, and has preferable characteristics. A ground electrode is formed on one side of a dielectric substrate, and spiral-shaped pattern electrodes are formed on the other side. Input/output electrodes are led out from intermediate portions of the pattern electrodes. Curved portions are formed between the input/output electrodes and the ends of the pattern electrodes. The ends of the pattern electrodes are positioned close to each other. Protective layers are formed on the ground electrode and pattern electrodes, which are laminated and integrated to form external electrodes. The ends of the pattern electrodes and the ground electrode are connected by one of the external electrodes.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: September 21, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshimi Kaneko, Kazuo Dougauchi, Katsuji Matsuta, Masahiko Kawaguchi
  • Patent number: 5612656
    Abstract: A resonator 10 includes a first dielectric substrate 12. An earth electrode 14 is formed almost entirely on one main surface of the first dielectric substrate 12. A first pattern electrode 16 and a first drawing electrode 18 are formed on the other main surface of the first dielectric substrate 12. The first pattern electrode 16 and the first drawing electrode 18 are covered with an insulation layer 20. A second pattern electrode 22 and a second drawing electrode 24 are formed on the insulation layer 20. The second pattern electrode 22 and the second drawing electrode 24 are covered with a protecting layer 26. The earth electrode 14 is covered with a protecting layer 28. The earth electrode 14, the first pattern electrode 16 and the second pattern electrode 22 are connected with each other through a terminal electrode 30a. Terminal electrodes 30b and 30c are connected to the earth electrode 14. A drawing terminal electrode 32 is connected to the first drawing electrode 18 and the second drawing electrode 24.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: March 18, 1997
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yukio Sakamoto, Toshimi Kaneko, Kazuo Dougauchi, Masahiko Kawaguchi, Katsuji Matsuta
  • Patent number: 5521564
    Abstract: A resonator comprises two dielectric substrates. A ground electrode and a U-shaped pattern electrode are formed respectively on the two surfaces of the first dielectric substrate. A take-out electrode is drawn out at a certain distance from one end of the pattern electrode, and is connected to the take-out terminal electrode. A guard electrode is formed opposite to the other end of the pattern electrode. A shield electrode is formed on a second dielectric substrate. The pattern electrode, the ground electrode and the shield electrode are connected by a terminal electrode. In addition, the guard electrode, the ground electrode and the shield electrode are connected by a terminal electrode. A chip-type filter can be obtained by forming a plurality of pattern electrodes on an dielectric substrate, and coupling them electromagnetically.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: May 28, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshimi Kaneko, Masahiko Kawaguchi, Katsuji Matsuta
  • Patent number: 5519366
    Abstract: A strip line filter has at least two strip lines and a common ground electrode, and on an end, has a solder ground terminal electrode and at least two link ground terminal electrodes at a distance from the solder ground terminal electrode. The solder ground terminal electrode is electrically connected with the common ground electrode, and the link ground terminal electrodes electrically connect each of the strip lines with the common ground electrode. Another strip line filter has at least two strip lines and a common ground electrode, and on an end, has a ground terminal electrode which has a solder portion and at least two arm portions extending from the solder portion. The ground terminal electrode is electrically connected with the common ground electrode via the solder portion and with the strip lines via the arm portions.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: May 21, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshimi Kaneko, Masahiko Kawaguchi, Katsuji Matsuta