Abstract: The video signal processor of the present invention comprises a CCD for storing an inputted image by converting it into an electric charge through photoelectrical conversion to be stored by each field and then outputting the stored electric charge by each field; a shutter pulse generator for supplying a shutter pulse which adjusts storage time of the electric charge in the CCD; and a variable controller for variably controlling adjusting amount of electric charge storage time by the shutter pulse by a field unit.

Abstract: When a time code signal corresponding to an image signal, to which a format conversion changing the number of frames per second is executed, is transmitted, information indicating a frame position where image data is changed through the format conversion in the image signal is attached to the time code signal to be transmitted. Alternatively, information indicating a synchronous state between frame conversion cycles in the format conversion and time code progression is attached to the time code signal. In the foregoing manner, a relationship between the frame position and the time code can be accurately grasped. Further, a secondary conversion (inverse conversion) is accurately executed to the image signal by means of the time code signal.

Abstract: Again controller gain controls digitalized video signals for each minimum video unit. A variation controller establishes video blocks each consisting of a plurality of minimum video units, and also establishes a gain control value of the gain controller for each of the minimum video units constituting the established video blocks. The gain controller sequentially divides the video signals into the video blocks and gain controls, based on the gain control values, the respective minimum video units constituting each of the divided digital video blocks. In this way, there can be obtained a visual effect equivalent to a conversion of video signals such as 24P video signals to video signals such as 60I video signals by use of a conversion format such as 2:3 pull down method. Moreover, such visual effect can be realized without necessity of any frame memories and without implementing any complex timing controls.

Abstract: The present invention comprises the step of reading a check-receiving data included in a transmitted time code signal and using the read check-receiving data to generate a transmitting side checking data, and the step of attaching the transmitting side checking data to the transmitted time code signal, as a pre-processing step at the time of transmitting the time code signal. The present invention comprises the step of reading the check-receiving data from the received time code signal and using the read check-receiving data to generate a receiving side checking data, and the step of reading the transmitting side checking data from the received time code signal and comparing the read transmitting side checking data to the receiving side checking data, thereby verifying whether or not an error is generated in the received time code signal. In this way, an error can be detected in the time code signal, as a post-processing step after the time code signal is received.

Abstract: When a time code signal corresponding to an image signal, to which a format conversion changing the number of frames per second is executed, is transmitted, information indicating a frame position where image data is changed through the format conversion in the image signal is attached to the time code signal to be transmitted. Alternatively, information indicating a synchronous state between frame conversion cycles in the format conversion and time code progression is attached to the time code signal. In the fore going manner, a relationship between the frame position and the time code can be accurately grasped. Further, a secondary conversion (inverse conversion) is accurately executed to the image signal by means of the time code signal.

Abstract: The video signal processor of the present invention comprises a CCD for storing an inputted image by converting it into an electric charge through photoelectrical conversion to be stored by each field and then outputting the stored electric charge by each field; a shutter pulse generator for supplying a shutter pulse which adjusts storage time of the electric charge in the CCD; and a variable controller for variably controlling adjusting amount of electric charge storage time by the shutter pulse by a field unit.

Abstract: The present invention comprises the step of reading a check-receiving data included in a transmitted time code signal and using the read check-receiving data to generate a transmitting side checking data, and the step of attaching the transmitting side checking data to the transmitted time code signal, as a pre-processing step at the time of transmitting the time code signal. The present invention comprises the step of reading the check-receiving data from the received time code signal and using the read check-receiving data to generate a receiving side checking data, and the step of reading the transmitting side checking data from the received time code signal and comparing the read transmitting side checking data to the receiving side checking data, thereby verifying whether or not an error is generated in the received time code signal. In this way, an error can be detected in the time code signal, as a post-processing step after the time code signal is received.