Patents by Inventor Katsujiro Tanzawa

Katsujiro Tanzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7700381
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7531462
    Abstract: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsujiro Tanzawa, Norihiko Tsuchiya, Junji Sugamoto, Yukihiro Ushiku
  • Patent number: 7510945
    Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: March 31, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nagano, Shinichi Nitta, Takashi Yamada, Tsutomu Sato, Katsujiro Tanzawa, Ichiro Mizushima
  • Publication number: 20080044983
    Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.
    Type: Application
    Filed: October 11, 2007
    Publication date: February 21, 2008
    Inventors: Hajime Nagano, Shinichi Nitta, Takashi Yamada, Tsutomu Sato, Katsujiro Tanzawa, Ichiro Mizushima
  • Patent number: 7314766
    Abstract: A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NH4F.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Sugamoto, Norihiko Tsuchiya, Yukihiro Ushiku, Katsujiro Tanzawa
  • Patent number: 7285825
    Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nagano, Shinichi Nitta, Takashi Yamada, Tsutomu Sato, Katsujiro Tanzawa, Ichiro Mizushima
  • Publication number: 20060281281
    Abstract: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 14, 2006
    Inventors: Katsujiro Tanzawa, Norihiko Tsuchiya, Junji Sugamoto, Yukihiro Ushiku
  • Publication number: 20060131696
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 22, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7057259
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Publication number: 20040150044
    Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.
    Type: Application
    Filed: April 7, 2003
    Publication date: August 5, 2004
    Inventors: Hajime Nagano, Shinichi Nitta, Takashi Yamada, Tsutomu Sato, Katsujiro Tanzawa, Ichiro Mizushima
  • Publication number: 20040137752
    Abstract: A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NH4F
    Type: Application
    Filed: November 13, 2003
    Publication date: July 15, 2004
    Inventors: Junji Sugamoto, Norihiko Tsuchiya, Yukihiro Ushiku, Katsujiro Tanzawa
  • Publication number: 20030003608
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: March 20, 2002
    Publication date: January 2, 2003
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 5688702
    Abstract: A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.
    Type: Grant
    Filed: January 24, 1994
    Date of Patent: November 18, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kazuyoshi Furukawa, Tsuneo Ogura, Katsujiro Tanzawa
  • Patent number: 5332920
    Abstract: A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: July 26, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kazuyoshi Furukawa, Tsuneo Ogura, Katsujiro Tanzawa
  • Patent number: 5097314
    Abstract: A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semicondcutor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: March 17, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kazuyoshi Furukawa, Tsuneo Ogura, Katsujiro Tanzawa
  • Patent number: 5049968
    Abstract: A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: September 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Kazuyoshi Furukawa, Tsuneo Ogura, Katsujiro Tanzawa
  • Patent number: 4878957
    Abstract: A dielectrically isolated semiconductor wafer substrate includes first and second semiconductive layers bonded to each other by a direct bonding technique in such a manner that an insulative layer is sandwiched therebetween. The first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, while the second semiconductive layer is a second silicon layer having a (111) crystal surface orientation. Thereafter, a peripheral portion of the resultant substrate is removed, and a substrate of a slightly smaller size is obtained which is provided with an additionally formed new orientation flat.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: November 7, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Yamaguchi, Kiminori Watanabe, Akio Nakagawa, Kazuyoshi Furukama, Kiyoshi Fukuda, Katsujiro Tanzawa