Abstract: An on-board vehicle display arrangement of a computer graphics device and two video cameras for generating left-viewpoint image and right-viewpoint image of vehicle guiding information, an image synthesizer for synthesizing the left-viewpoint image and right-viewpoint image by alternately arranging their elements by pixel, and a stereoscopic display for separately displaying a left-viewpoint image and a right-viewpoint image of the synthesized image, which images are provided inside the vehicle to display a stereoscopic image with outside information taken through the video cameras, vehicle travel guiding information generated by the computer graphics device according to navigation data, presumed travelling information generated by the computer graphics device according to a prospective running condition estimated from the results of detection of current driving conditions of the vehicle.

Abstract: A semiconductor sensor has a plurality of field-effect transistors disposed on a semiconductor substrate at spaced intervals. The field-effect transistors have respective drains electrically connected parallel to each other, respective sources electrically connected parallel to each other, and gates electrically connected parallel to each other. While a gate bias voltage is being applied to each of the field-effect transistors, a stress applied to the semiconductor substrate is detected based on a change in a combined output of the field-effect transistors. A single comb-shaped field-effect transistor or a single planar type field-effect transistor may be employed instead of the plurality of field-effect transistors.

Abstract: A semiconductor stress sensor includes a field-effect transistor for producing a drain current commensurate with a stress applied thereto. The gate of the field-effect transistor is supplied with a gate bias voltage from a gate bias voltage generator. The drain current from the field-effect transistor is converted into a detected output signal by a current-to-voltage converter. The gate-to-source voltage of the field-effect transistor can be varied to reduce the drain current in a standby mode when no stress is to be detected. To vary the gate-to-source voltage, the gate bias voltage applied to the gate of the field-effect transistor may be slightly varied or the source potential thereof may be slightly varied. The gate-to-source voltage of the field-effect transistor slightly differ from each other in the standby and stress sensing modes. Even in the standby mode, the field-effect transistor is supplied with substantially the same voltage as in the stress sensing mode.

Abstract: A semiconductor memory device includes a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of word lines interconnecting the memory cells in the row direction and a plurality of bit line pairs interconnecting the memory cells in the column direction. One end of each bit line pair is connected to a clamping circuit, while the other end of each bit line pair is connected via a column select gate to a read/write circuit. Each bit line pair is bent about centrally in the two-dimensional form of a letter U and the clamping circuit and the column select gate are disposed alternately on one same straight line.

Abstract: A semiconductor sensor has a plurality of field-effect transistors disposed on a semiconductor substrate at spaced intervals. The field-effect transistors have respective drains electrically connected parallel to each other, respective sources electrically connected parallel to each other, and gates electrically connected parallel to each other. While a gate bias voltage is being applied to each of the field-effect transistors, a stress applied to the semiconductor substrate is detected based on a change in a combined output of the field-effect transistors. A single comb-shaped field-effect transistor may be employed instead of the plurality of field effect transistors.

Abstract: A high resistance/load type memory cell of a static semiconductor memory device includes two load elements, two driver transistors, and two access transistors. The threshold voltage of each driver transistor is set at a high value so that the OFF resistance value of the driver transistor is 10 to 100 times the resistance value of each load resistance. The threshold voltage of each access transistor is set to be lower than the threshold voltage of each driver transistor so that the OFF resistance value of the access transistor is twice to 10 times the resistance value of each load resistance. Thus, power consumption in a standby state is reduced, while data holding characteristics of the memory cell are stabilized in selected and non-selected states.

Abstract: A memory cell array of this semiconductor memory device is divided into a plurality of large memory cell groups, and each of the large memory cell groups is further divided into a plurality of small memory cell groups. A plurality of main row-selecting lines, a plurality of sub row-selecting lines and a plurality of word lines are provided in the memory cell array, each of the large memory cell groups and each of the small memory cell groups, respectively. Main global decoders select one of the main row-selecting lines in response to an internal address signal. Sub global decoders select a sub row-selecting line associated with the selected main row-selecting line in the large memory cell group selected by a large memory cell group selecting signal. Local decoders select a word line associated with the selected sub row-selecting line in the small memory cell group selected by a small memory cell group selecting signal.

Abstract: A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.

Abstract: A semiconductor memory device in which an output data bus (14) is precharged at a middle potential level prior to reading out data. A Schmidt Trigger circuit (39) having a hysteresis loop in input-output characteristics is provided between the output data bus (14) and a data output buffer (15). This allows the data output buffer (15) to maintain a stable output (16) while precharging the data bus (14).

Abstract: A semiconductor differential amplifier includes first and second MOS transistors of a first conductivity type acting as driver transistors, and third through sixth MOS transistors of a second conductivity type acting as load transistors. First and second input terminals are respectively connected to gate terminals of the first and fifth, and second and sixth transistors. Therefore, since input signals are applied to transistors of both the load and driver sections of the amplifier, the amplifier exhibits a higher sensitivity for detecting relatively small differences between the voltage at the first input terminal and the voltage at the second input terminal.

Abstract: A semiconductor memory device includes a plurality of memory cell rows each including a plurality of memory cells; a plurality of row selection signal lines each for transmitting a row selection signal to the memory cells of each memory cell row; and a row decoder for giving a row selection signal to the row selection signal line connected to the memory cells on a memory cell row in accordance with the row address input externally, wherein the row selection signal is at a power supply voltage level during a reading-out period, an intermediate voltage level between the power supply voltage and a ground level during the writing-in period, and the ground level at periods other than the writing-in and reading-out periods.

Abstract: A constant voltage generating circuit comprises a power supply terminal (1), an output terminal (2), a p-channel MOS FET (3), n-channel MOS FET's (4 and 5) and resistors (8 and 9). A node C of the resistors (8) and (9) is connected to a control terminal of the n-channel MOS FET (4), whereby the potential in the output terminal (2) is determined mainly by the threshold voltage of the n-channel MOS FETs (4) and (5), a ratio of the resistance values of the resistors (8) and (9) and a degree of conduction of the n-channel MOS FET (4). Instead of the resistors (8) and (9), n-channel MOS FET's (10 and 11) may be provided so as to compensate for the influence of power supply voltage in the output voltage by changing the impedance of the n-channel MOS FET (10) according to the change of the voltage of the power supply terminal (1).