Patents by Inventor Katsuki Matsudera
Katsuki Matsudera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220300438Abstract: A semiconductor memory device includes a plurality of first chips and a second chip. The second chip is connected to the first chips via M second channels. Upon receipt of first data via the first channel at a transfer rate N times higher than the transfer rate per a single second channel, the second chip transmits the first data to the N first chips in parallel via the N second channels by sorting the first data into N pieces in a unit of bus width of the first channel. Upon receipt of L pieces of third data in parallel from L of the M second channels, the second chip sequentially concatenates the L pieces of third data in a unit of bus width of the first channel and transmits the data via the first channel at the transfer rate L times higher the transfer rate per the single second channel.Type: ApplicationFiled: September 9, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Goichi OOTOMO, Katsuki MATSUDERA
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Patent number: 11183256Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.Type: GrantFiled: June 29, 2020Date of Patent: November 23, 2021Assignee: Kioxia CorporationInventors: Koichi Shinohara, Katsuki Matsudera, Ian Christopher Gamara, Yoshikazu Harada, Noritaka Kai, Yusuke Tanefusa
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Publication number: 20210082531Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.Type: ApplicationFiled: June 29, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Koichi SHINOHARA, Katsuki MATSUDERA, Ian Christopher GAMARA, Yoshikazu I HARADA, Noritaka KAI, Yusuke TANEFUSA
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Patent number: 10346068Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.Type: GrantFiled: August 31, 2017Date of Patent: July 9, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Ishii, Yuji Nagai, Yukihiro Utsuno, Katsuki Matsudera
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Publication number: 20180246660Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.Type: ApplicationFiled: August 31, 2017Publication date: August 30, 2018Inventors: Hiroyuki ISHII, Yuji NAGAI, Yukihiro UTSUNO, Katsuki MATSUDERA
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Patent number: 9665426Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.Type: GrantFiled: November 19, 2015Date of Patent: May 30, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jiezhi Chen, Kuniharu Takahashi, Hiroyuki Nagashima, Yuichiro Mitani, Katsuki Matsudera, Kazunori Kanebako
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Publication number: 20160217035Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.Type: ApplicationFiled: November 19, 2015Publication date: July 28, 2016Inventors: Jiezhi CHEN, Kuniharu Takahashi, Hiroyuki Nagashima, Yuichiro Mitani, Katsuki Matsudera, Kazunori Kanebako
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Patent number: 8648628Abstract: According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.Type: GrantFiled: September 21, 2011Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junichiro Shirai, Katsuki Matsudera
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Patent number: 8384441Abstract: A semiconductor integrated circuit has a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison. The semiconductor integrated circuit has a first switch circuit between a first reception terminal and the first noninverting input terminal. The semiconductor integrated circuit has a second switch circuit between a second reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a third switch circuit between the first reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a fourth switch circuit between the second reception terminal and the first noninverting input terminal.Type: GrantFiled: January 19, 2011Date of Patent: February 26, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Katsuki Matsudera
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Publication number: 20120194225Abstract: According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.Type: ApplicationFiled: September 21, 2011Publication date: August 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junichiro Shirai, Katsuki Matsudera
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Patent number: 8030961Abstract: A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.Type: GrantFiled: September 3, 2010Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Katsuki Matsudera
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Publication number: 20110181321Abstract: A semiconductor integrated circuit has a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison. The semiconductor integrated circuit has a first switch circuit between a first reception terminal and the first noninverting input terminal. The semiconductor integrated circuit has a second switch circuit between a second reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a third switch circuit between the first reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a fourth switch circuit between the second reception terminal and the first noninverting input terminal.Type: ApplicationFiled: January 19, 2011Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuki Matsudera
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Publication number: 20100327904Abstract: A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuki Matsudera
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Patent number: 7843089Abstract: A semiconductor device comprises a board; a semiconductor chip; a memory controller operative to control the semiconductor chip; and a power supply chip having a capacitor. The semiconductor chip is stacked on the board. The memory controller and the power supply chip are stacked on the semiconductor chip. The capacitor is used to stabilize the voltage applied to the semiconductor chip.Type: GrantFiled: July 19, 2007Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mikihiko Ito, Masaru Koyanagi, Katsuki Matsudera
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Patent number: 7808269Abstract: A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.Type: GrantFiled: June 26, 2008Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Katsuki Matsudera
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Publication number: 20100026397Abstract: A PLL circuit includes a VCO circuit that generates an output clock having a frequency corresponding to potential of a first control voltage signal input from an LPF at a pre-stage, using a ring oscillator in which M delay circuits having delay times changing according to a control voltage input to a control terminal are connected in a ring shape. The VCO circuit includes a low-pass filter that extracts a second control voltage signal in a low frequency band from the first control voltage signal, and, in the ring oscillator. The first control voltage signal is input to control terminals of m (m<M) delay circuits among the M delay circuits and the second control voltage signal is input to control terminals of (M?m) delay circuits.Type: ApplicationFiled: June 30, 2009Publication date: February 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuki Matsudera
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Publication number: 20090039913Abstract: A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.Type: ApplicationFiled: June 26, 2008Publication date: February 12, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuki Matsudera
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Patent number: 7368939Abstract: A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.Type: GrantFiled: March 29, 2006Date of Patent: May 6, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Mikihiko Ito, Katsuki Matsudera
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Publication number: 20080019203Abstract: A semiconductor device comprises a board; a semiconductor chip; a memory controller operative to control the semiconductor chip; and a power supply chip having a capacitor. The semiconductor chip is stacked on the board. The memory controller and the power supply chip are stacked on the semiconductor chip. The capacitor is used to stabilize the voltage applied to the semiconductor chip.Type: ApplicationFiled: July 19, 2007Publication date: January 24, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikihiko ITO, Masaru Koyanagi, Katsuki Matsudera
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Patent number: 7206242Abstract: A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.Type: GrantFiled: December 17, 2004Date of Patent: April 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuki Matsudera, Kazuhide Yoneya, Masaru Koyanagi