Abstract: According to one exemplary embodiment, an information processing apparatus includes: a first memory including a first plurality of areas each having a first memory capacity; a second memory including a second plurality of areas each having a second memory capacity that is larger than the first memory capacity; a selector configured to select a first area of the first memory; and a writing module that is configured to (i) write data from area(s) of the first memory to a first area of the second plurality of areas of the second memory if the area(s) of the first plurality of areas is in a first data storage state, and (ii) refrain from writing data from a remaining area(s) of the first memory to the second memory if the remaining area(s) is in a second data storage state different from the first data storage state.

Abstract: According to one exemplary embodiment, an information processing apparatus includes: a first memory having plural management areas managed in units of a first memory capacity; a second memory to which data is written in units of a second memory capacity larger than the first memory capacity; a selector which selects one first management area of the plural management areas; and a writing module which writes data of a number, corresponding to the second memory capacity, of management areas to the second memory, the data including data of the first management area and data of different management areas from the first management area. If after data of the first management area and the different management areas are written to the second memory the selector selects one second management area of the different management areas, the writing module refrains from writing data of the second management area to the second memory.

Abstract: According to one embodiment, a data writing apparatus includes a memory and write module. The memory includes a storage area including a physical block having a data area and redundancy area. The write module is configured to write a data block obtained by dividing data, in the data area of the physical block. In addition, the write module is configured to write a first data block in a first data area which is the data area of a first physical block, write a second data block as a data block to be read before the first data block when reading the data, in a second data area which is the data area of a second physical block, and write information indicating the first physical block in the redundancy area of the second physical block.

Abstract: According to one embodiment, a program execution apparatus includes a first memory configured to store a first program, a second memory configured to store a partial program loaded from the first memory or a second program loaded from one other memory, and a controller configured to perform first correspondence to cause a first storage region of the first program in the first memory to correspond to a first virtual region of a virtual memory, execute the first program stored in the first memory on the basis of the first correspondence according to a request for the execution of the first program.

Abstract: An electronic apparatus includes a clock oscillator which supplies a clock signal, a processor which generates an internal clock on the basis of the clock signal supplied from the clock oscillator, and a control unit which controls a frequency of the internal clock in accordance with a ratio of an executable instruction count per unit time to a clock count per unit time of the internal clock generated by the processor.

Abstract: Compressed data is written from a main memory into a cache memory. The capacity of decompressed data corresponding to the compressed data is calculated. To ensure that cache mis does not occur upon subsequent data writing, an address of a location in which the decompressed data is to be stored is written into the cache memory. A data area for the calculated amount of data is ensured in the cache memory. The compressed data stored in the cache memory is decompressed and then written into the area ensured in the cache memory. The decompressed data stored in the cache memory is moved to the main memory by means of a cache memory controller.

Abstract: An electric apparatus executes a plurality of tasks including a real-time task for executing real-time processing. The electric apparatus includes a processor, a unit which executes a scheduling process of preferentially assigning the real-time task to the processor in accordance with schedule information for controlling an execution sequence of the tasks, a sensor which senses the temperature of the processor, and a unit which executes, if the temperature of the processor sensed by the sensor is higher than a given threshold value, a process of assigning a processor stop task to the processor to periodically execute the processor stop task in a time except for an execution term of the real-time task.

Abstract: In a disk storage apparatus for accessing a disk drive according to a data access request accompanied by recording or reproduction from plural applications, a disk driver secures a buffer area for guaranteeing a predetermined throughput in a memory according to a data access request accompanied by recording or reproduction from the plural applications. The disk driver issues a command corresponding to each data access request to the disk drive so as to control read/write access of stream data.

Abstract: An electronic apparatus includes a clock oscillator which supplies a clock signal, a processor which generates an internal clock on the basis of the clock signal supplied from the clock oscillator, and a control unit which controls a frequency of the internal clock in accordance with a ratio of an executable instruction count per unit time to a clock count per unit time of the internal clock generated by the processor.