Patents by Inventor Katsumi Andou

Katsumi Andou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040254776
    Abstract: A delay time calculation method and a delay time calculation system for a semiconductor integrated circuit that enables timing testing to be efficiently performed. The propagation delay time for a signal path taking into consideration variations in the chip is calculated based on a corrected variation coefficient. The corrected value of the variation coefficient is calculated based on a function that approximates the propagation delay time caused by variations in the chip as a propagation delay time affected by the actual variations in the chip in accordance with the number of cell stages in the signal path. Accordingly, the propagation delay time is calculated to have an appropriate occurrence probability corresponding to a 3&sgr; range in the probability density distribution.
    Type: Application
    Filed: July 9, 2004
    Publication date: December 16, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Katsumi Andou
  • Patent number: 6218975
    Abstract: An interleaved auto-zero analog-to-digital converter includes chopper comparators for comparing an analog input signal to predetermined voltage values. An additional chopper comparator is included for performing the comparison function of a chopper comparator undergoing an auto zero operation.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventors: Sanroku Tsukamoto, Katsumi Andou
  • Patent number: 5559765
    Abstract: A data access controller for a disc device is disclosed for accessing data on a disc. A control unit, controlling the disc device, outputs a mode switching signal. A mark detector detects the sector mark and the address mark in read data from a target sector, and outputs a first and second detection signals indicative of the detections of the sector mark and address mark, respectively. In response to the mode switching signal, the mark detector enters a first search mode to detect all data bits of the target sector. A physical address read circuit reads physical address data in the read data in response to the second detection signal, and outputs a synchronizing signal. The format counter receives a basic clock signal to count the number of pulses of the clock signal, and resets its count value to a prescribed value in accordance with the first detection signal and the synchronizing signal to synchronize its count value with the position of the drive head on the target sector.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: September 24, 1996
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Katsumi Andou