Patents by Inventor Katsumi Egashira

Katsumi Egashira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170069568
    Abstract: According to an embodiment, a capacitor includes a first electrode, a second electrode and a first via. The first electrode is provided in a first interconnect layer. The second electrode is provided in the first interconnect layer and surrounds a periphery of the first electrode by a closed circuit. The first via is connected to the first electrode and provided to pass through the first interconnect layer.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 9, 2017
    Inventors: Ken INAZUMI, Hiroto OHNO, Katsumi EGASHIRA
  • Patent number: 7037738
    Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Sugiyama, Kenichi Ohashi, Atsuko Yamashita, Shoichi Washizuka, Yasuhiko Akaike, Shunji Yoshitake, Koji Asakawa, Katsumi Egashira, Akira Fujimoto
  • Publication number: 20050145864
    Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 7, 2005
    Inventors: Hitoshi Sugiyama, Kenichi Ohashi, Atsuko Yamashita, Shoichi Washizuka, Yasuhiko Akaike, Shunji Yoshitake, Koji Asakawa, Katsumi Egashira, Akira Fujimoto
  • Publication number: 20030178626
    Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.
    Type: Application
    Filed: January 17, 2003
    Publication date: September 25, 2003
    Inventors: Hitoshi Sugiyama, Kenichi Ohashi, Atsuko Yamashita, Shoichi Washizuka, Yasuhiko Akaike, Shunji Yoshitake, Koji Asakawa, Katsumi Egashira, Akira Fujimoto
  • Patent number: 6593627
    Abstract: A semiconductor wafer has a first element forming section, a second element forming section adjoining the first element forming section, and a third element forming section adjoining the second element forming section. The first element forming section has a first supporting substrate, a first buried insulating film formed on the first supporting substrate, and a first active layer formed on the first buried insulating film. The second element forming section has a second supporting substrate, a second buried insulating film formed on the second supporting substrate, and a second active layer formed on the second buried insulating film. The second active layer has a thickness being different from a thickness of the first active layer. The third element forming section has a third active layer.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: July 15, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsumi Egashira
  • Publication number: 20020142507
    Abstract: A semiconductor wafer has a first element forming section, a second element forming section adjoining the first element forming section, and a third element forming section adjoining the second element forming section. The first element forming section has a first supporting substrate, a first buried insulating film formed on the first supporting substrate, and a first active layer formed on the first buried insulating film. The second element forming section has a second supporting substrate, a second buried insulating film formed on the second supporting substrate, and a second active layer formed on the second buried insulating film. The second active layer has a thickness being different from a thickness of the first active layer. The third element forming section has a third active layer.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsumi Egashira
  • Publication number: 20020038874
    Abstract: A hetero-bipolar transistor comprises: a first-conductive-type Si semiconductor substrate layer; a first Si1-xGex layer (0<x<1) formed on the first-conductive-type Si semiconductor substrate, the first Si1-xGex layer being doped with a first-conductive-type impurity; a second Si1-xGex layer formed on the first Si1-xGex layer, the second Si1-xGex layer being doped with a second-conductive-type impurity; and a Si layer formed on the second Si1-xGex layer, the Si layer being doped with the first-conductive-type impurity by a concentration higher than that of the second-conductive-type impurity.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 4, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsumi Egashira