Abstract: A fluorine-containing ether compound represented by the following formula (1) is provided. R1—CH2—R2—CH2—R3 (1) (In the formula (1), R1 is an alkoxy group having 1 to 10 carbon atoms, R2 is a perfluoropolyether chain, R3 is —OCH2CH(OH)CH2O(CH2)mOH (in in the formula is an integer of 2 to 4).

Abstract: An erroneous operation preventing circuit of an electrically rewritable non-volatile memory device is for setting one or more operational modes of a plurality of operational modes including at least a first reading mode of reading out data from a memory array 4, a programming mode, an erasing mode and a second reading mode of reading out data not stored in the memory array 4, in accordance with an input control command, and for performing a predetermined process in the set operational modes. The erroneous operation preventing circuit comprises an operational mode enforcing circuit 2a for setting the first reading mode regardless of the input of the control command, in a data protection status where the programming mode and the erasing mode are inhibited from being set in accordance with a control signal for protecting predetermined data.

Abstract: The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

Abstract: The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

Abstract: A data management system and method use link information stored with a plurality of data segments. The data management system includes: a nonvolatile semiconductor storage section including a plurality of blocks; a storage control section; a data management system control section for processing data to be stored in the nonvolatile semiconductor storage section; and a data management system memory section for storing management data. The data management system control section performs data management by dividing the data into data segments in units of a sector which is a logical unit for data management; storing data link information which indicates the ordinal relationship of the data segments, together with the data segments, in the nonvolatile semiconductor storage section; and storing, as link information in each sector, information about immediately-previous and immediately-subsequent data storage sites.

Abstract: There is provided an erroneous operation preventing circuit for preventing erroneous operation of reading out erroneous data in a circuit due to system noises, etc. when data in a memory array should be read out. The erroneous operation preventing circuit of an electrically rewritable non-volatile memory device for setting one or more operational modes of a plurality of operational modes including at least a first reading mode of reading out data from a memory array 4, a programming mode, an erasing mode and a second reading mode of reading out data not stored in the memory array 4, in accordance with an input control command, and for performing a predetermined process in the set operational modes, comprises an operational mode enforcing circuit 2a for setting the first reading mode regardless of the input of the control command, in a data protection status where the programming mode and the erasing mode are inhibited from being set in accordance with a control signal for protecting predetermined data.

Abstract: A data management system includes: a nonvolatile semiconductor storage section including a plurality of blocks capable of storing data; a storage control section for controlling a storage operation of the nonvolatile semiconductor storage section; a data management system control section for processing data to be stored in the nonvolatile semiconductor storage section; and a data management system memory section for storing management data which is referred to by the data management system control section, wherein the data management system control section performs data management by: dividing the data into data segments by units of a sector which is a logical unit for data management; storing data link information which indicates the ordinal relationship of the data segments, together with the data segments, in the nonvolatile semiconductor storage section via the storage control section; and storing, as link information in each sector, information about immediately-previous and immediately-subsequent data s

Abstract: A non-volatile semiconductor memory device includes a memory cell array capable of storing data in volatile and non-volatile states, and a determination circuit for determining whether a row address in a current cycle is the same as that in a previous cycle. When the row address in the current cycle is different from that in the previous cycle, a store operation is performed, where volatile data is stored in the memory cell as non-volatile data; thereafter a recall operation is performed where non-volatile data stored in the memory cell is transformed into volatile data; the resulting volatile data is stored in the memory cell and a sense amplifier, or at least one of the sense amplifier and a latch circuit. When the row address in the current cycle is the same as that in the previous cycle, a read or write operation is performed with respect to volatile data stored in the memory cell, the sense amplifier or latch circuit, but non-volatile data is not read from or written to the memory cell.

Abstract: In a non-volatile flash memory having memory cells divided into blocks, a command state machine decodes a refresh command entered, and sends a decoded result to a write state machine. The write state machine performs a refresh operation in accordance with the decoded result. The nonvolatile flash memory allows a user to enter the refresh command. The refresh command includes “SINGLE BLOCK REFRESH”, “FULL CHIP REFRESH”, “REFRESH SUSPEND”, and “REFRESH RESUME”.

Abstract: An electrically rewritable nonvolatile semiconductor memory device made in accordance with a preferred embodiment of this invention, includes CAM data setting means for storing CAM data electrically written therein, wherein the CAM data is received from an external source; address fixing means for fixing a signal level of a portion of an internal address corresponding to an external address input from an external source based on the CAM data set in the CAM data setting means; and address switch means for switching a corresponding relationship between a portion of the external address input from an external source and a portion of the internal address based on the CAM data set in the CAM data setting means.

Abstract: A nonvolatile semiconductor memory device including: a memory cell array for storing data therein in a nonvolatile manner; block protect data storage regions provided for the respective blocks, for storing data therein in a nonvolatile manner; and block protect means for disabling an erase and a write of data from/into a block, if block protect data has been stored in the block protect data storage region of the block and a write protect signal has been activated.

Abstract: An electrically erasable and rewritable semiconductor memory device including at least one memory block, comprising: a WP signal generator for generating a WP signal for controlling protection of data stored in the memory block; a protect state setting section for setting a protect state for the memory block, the data stored in the memory block being protectable from erase/write operations when the protect state is set to the memory block; and a data protecting section for prohibiting the erase/write operations for the memory block to which the protect state is set, in the case where the WP signal is active.

Abstract: A memory device including a memory for storing data having volatile and non-volatile capability; an access circuit for reading/writing the data stored in a volatile state at an address in said memory in accordance with an access command indicating the address; a transfer circuit for transferring the data stored in said memory from the volatile state into a non-volatile state; and a recall circuit for recalling the data stored in said memory in the non-volatile state into the volatile state, wherein said recall circuit selectively performs a recall operation for a section of said memory which includes the address before said access circuit performs a read/write operation for the data when the data at the address is stored in the non-volatile state.

Abstract: The presently claimed NVDRAM including: volatile memory cells which require a refreshing operation; non-volatile memory cells; an address generation circuit for automatically generating in sequence respective addresses; a self-refresh circuit; a refresh timing circuit; a self-store starting circuit for determining whether the duration of the refreshing operation as measured by the refresh timing circuit has exceeded the predetermined time amount; a self-store circuit for, when the duration of the refreshing operation has exceeded the predetermined time amount, stopping the refreshing operation as measured by the refresh timing circuit and for sequentially transferring the content stored in the volatile memory cells to the non-volatile memory cells to be stored therein based on the addresses generated by the address generation circuit.

Abstract: In accordance with the levels of input signals, a recall signal or store signal is generated and held. Based on the signal currently held, only one of the read/write timing circuit, recall timing circuit and store timing circuit is enabled for operation with the operation of the other two timing circuit disabled: the recall timing circuit is enabled when the recall signal is held, the store timing circuit when the store signal is held, and the read/write timing circuit when neither the recall signal nor the store signal is held. Therefore, once one operation mode has been selected by setting the input signals to a prescribed combination of levels, the selected mode is held until another operation mode is selected. Since there is no need to input the nonvolatile enable signal NE signal during the recall operation, the external input timing can be simplified.

Abstract: A non-volatile dynamic random access memory device which includes a memory section including at least non-volatile memory cells for a non-volatile mode operation which includes a recall operation and a store operation; and a rewriting device for rewriting data when the power is turned on. The data is identical with data stored in the memory section.

Abstract: An NVDRAM memory device which performs a recall operation in which non-volatile data stored in memory cell is converted to volatile data in a recall mode, a store operation in which the volatile data stored in the memory cell is converted to the non-volatile data in a store mode, and a read/write operation in which the volatile data stored in the memory cell is read or written in a DRAM mode, includes: a counter circuit for counting the number of the recall or store operations, which generates an inhibit signal in the case where a counted value exceeds a predetermined value and resets the counted value in response to an external reset signal; and an inhibit unit for inhibiting the recall or store operation in response to the inhibit signal given from the counter circuit.

Abstract: In the normal selfrefresh mode, the timer output selection circuit selects the timer output of a longer cycle from the timer outputs generated by the internal timer circuit, and the selected timer output supplied as an operation activation signal for the selfrefresh operation. Using this long timer output, the selfrefresh operation of DRAM cells in the memory device is performed with a low operating current which allows the memory device to be backed up by a battery. When the selfrefresh mode is set before the store operation, the timer output of a short cycle is selected from the timer outputs generated by the internal timer circuit, and the short timer output is supplied as an operation activation signal for the selfrefresh operation. Using this short timer output, the selfrefresh operation of the volatile memory means is performed.

Abstract: A semiconductor memory device having memory cells in which a DRAM section and an EEPROM section are combined, and a transistor for transferring data between the DRAM and EEPROM sections is disclosed. The DRAM section includes a MOS transistor, and a capacitor one electrode of which is connected to the source of the MOS transistor. The EEPROM section has a floating gate transistor. The transistor for transfer is connected between the source of the MOS transistor and the source/drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. Methods of rewriting and recalling data in the semiconductor memory device are also disclosed. The methods can be performed without shortening the life of the EEPROM section.

Abstract: A method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell. The DRAM node of the NVDRUM cell is charged to a high potential and allowed to discharge through the EEPROM transistor. Since the gate of the EEPROM is tied to the DRAM node, the DRAM node voltage, which is also the EEPROM gate-to-source voltage, will, if the NVDRAM is left alone, drop until the EEPROM transistor shuts off. The EEPROM gate-to-source voltage at any point in time along this discharge path is measured through an iterative process. First, timing signals are adjusted to specify the point in time at which the EEPROM voltage is to be measured. Then, during each iteration, the EEPROM voltage is charged up and allowed to the discharge. At the point in time along the discharge path specified by the timing signals, a reference voltage is compared with the EEPROM voltage to determine if the reference voltage is above or below the EEPROM voltage.