Patents by Inventor Katsumi Horiguchi

Katsumi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7767055
    Abstract: A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode and a second electrode are disposed opposite each other. An RF power supply is disposed to supply an RF power to the first or second electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma. The target substrate is supported by a support member between the first and second electrodes such that a process target surface thereof faces the second electrode. A conductive functional surface is disposed in a surrounding region around the plasma generation region and grounded to be coupled with the plasma in a sense of DC to expand the plasma.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: August 3, 2010
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Shinji Himori, Noriaki Imai, Katsumi Horiguchi, Takaaki Nezu, Shoichiro Matsuyama, Hiroki Matsumaru, Toshihiro Hayami, Kazuya Nagaseki, Itsuko Sakai, Tokuhisa Ohiwa, Yoshikazu Sugiyasu
  • Patent number: 7678225
    Abstract: A focus ring for a plasma processing apparatus has an inner region, middle region, and outer region, disposed in this order from the inner side to surround a target substrate. On the side to be exposed to plasma, the surfaces of the inner region and outer region consist essentially of a dielectric, while the surface of the middle region consists essentially of a conductor. The middle region is arranged to shift the peak of plasma density to the outside of the peripheral edge of the target substrate. If there is no middle region, the peak of plasma density appears substantially directly above the peripheral edge of the target substrate.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: March 16, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Takaaki Nezu, Katsumi Horiguchi, Daisuke Hayashi, Toshiya Tsukahara
  • Publication number: 20080261406
    Abstract: An etching method capable of increasing the selectivity of a polysilicon film to a silicon oxide film and suppressing recess formation on a silicon base layer. That part of the polysilicon film of a wafer transferred into a processing vessel which is exposed through an opening is etched so as to slightly remain on a gate oxide film. The pressure in a processing space is set to 66.7 Pa, HBr gas and He gas are supplied to the processing space, and a microwave of 2.45 GHz is supplied to a radial line slot antenna. The polysilicon film is etched by plasma generated from the HBr gas so as to be completely removed, the exposed gate oxide film is etched, and a resist film and an anti-reflection film are etched.
    Type: Application
    Filed: September 26, 2007
    Publication date: October 23, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Etsuo IIJIMA, Katsumi Horiguchi
  • Patent number: 7416676
    Abstract: A plasma etching method for etching an etching target layer of a silicon layer through a mask of a silicon oxide film includes the following sequential steps of forming an opening in the silicon oxide film, wherein an opening dimension of a portion between a top and a bottom surface of the mask is enlarged compared to opening dimensions of the top and the bottom surface of the mask and etching the silicon layer by using a halogen containing gas. A gaseous mixture containing HBr gas, NF3 gas and O2 gas is used as the halogen containing gas. A hole or a trench having an opening diameter or an opening width equal to or smaller than 0.2 ?m is formed in the etching target layer. Further, a hole or a trench having an aspect ratio equal to or greater than forty is formed in the etching target layer.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: August 26, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Jin Fujihara, Katsumi Horiguchi
  • Patent number: 7109123
    Abstract: A Si etching method etches a Si wafer held on a susceptor placed in a processing vessel by a plasma-assisted etching process. A mixed etching gas prepared by mixing fluorosulfur gas, such as SF6 gas, or fluorocarbon gas, O2 gas and fluorosilicon gas, such as SiF4 gas is supplied into the processing vessel. RF power of 40 MHz or above is applied to the mixed etching gas to generate a plasma. The Si wafer is etched with radicals and ions contained in the plasma.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: September 19, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Takanori Mimura, Kazuya Nagaseki, Kenji Yamamoto, Katsumi Horiguchi, Yahui Huang
  • Publication number: 20060180571
    Abstract: A plasma etching method for etching an etching target layer of a silicon layer through a mask of a silicon oxide film includes the following sequential steps of forming an opening in the silicon oxide film, wherein an opening dimension of a portion between a top and a bottom surface of the mask is enlarged compared to opening dimensions of the top and the bottom surface of the mask and etching the silicon layer by using a halogen containing gas. A gaseous mixture containing HBr gas, NF3 gas and O2 gas is used as the halogen containing gas. A hole or a trench having an opening diameter or an opening width equal to or smaller than 0.2 ?m is formed in the etching target layer. Further, a hole or a trench having an aspect ratio equal to or greater than forty is formed in the etching target layer.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 17, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jin Fujihara, Katsumi Horiguchi
  • Publication number: 20060118044
    Abstract: A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode and a second electrode are disposed opposite each other. An RF power supply is disposed to supply an RF power to the first or second electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma. The target substrate is supported by a support member between the first and second electrodes such that a process target surface thereof faces the second electrode. A conductive functional surface is disposed in a surrounding region around the plasma generation region and grounded to be coupled with the plasma in a sense of DC to expand the plasma.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 8, 2006
    Inventors: Shinji Himori, Noriaki Imai, Katsumi Horiguchi, Takaaki Nezu, Shoichiro Matsuyama, Hiroki Matsumaru, Toshihiro Hayami, Kazuya Nagaseki, Itsuko Sakai, Tokuhisa Ohiwa, Yoshikazu Sugiyasu
  • Publication number: 20050014372
    Abstract: When etching a silicon layer 210 with a processing gas containing a mixed gas constituted of HBr gas, and O2 gas and SiF4 gas and further mixed with both of or either of SF6 gas and NF3 gas by using a pre-patterned mask having a silicon oxide film layer 204 inside an airtight processing container 102, high-frequency power with a first frequency is applied from a first high-frequency source 118 and high-frequency power with a second frequency lower than the first frequency is applied from a second high-frequency source 138 to a lower electrode 104 on which a workpiece is placed. Through this etching process, holes or grooves achieving a high aspect ratio are formed in a desirable shape at the silicon layer.
    Type: Application
    Filed: June 25, 2004
    Publication date: January 20, 2005
    Inventors: Satoshi Shimonishi, Takanori Matsumoto, Katsumi Horiguchi, Kenji Yamamoto, Fumihiko Higuchi
  • Publication number: 20040222190
    Abstract: In a plasma processing method, a silicon layer of an object to be processed is etched by using a plasma of a processing gas introduced into an airtight processing chamber through a patterned mask. The processing gas contains a gaseous mixture of HBr, O2 and SiF4 and, additionally, one or both of SF6 gas and NF3 gas; and a gas containing C and F is further added to the processing gas.
    Type: Application
    Filed: March 31, 2004
    Publication date: November 11, 2004
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Katsumi Horiguchi, Kenji Yamamoto, Kiyohito Ito, Keiichi Kanno
  • Publication number: 20040097090
    Abstract: A Si etching method etches a Si wafer held on a susceptor placed in a processing vessel by a plasma-assisted etching process. A mixed etching gas prepared by mixing fluorosulfur gas, such as SF6 gas, or fluorocarbon gas, O2 gas and fluorosilicon gas, such as SiF4 gas is supplied into the processing vessel. RF power of 40 MHz or above is applied to the mixed etching gas to generate a plasma. The Si wafer is etched with radicals and ions contained in the plasma.
    Type: Application
    Filed: August 26, 2003
    Publication date: May 20, 2004
    Inventors: Takanori Mimura, Kazuya Nagaseki, Kenji Yamamoto, Katsumi Horiguchi, Yahui Huang
  • Publication number: 20040074605
    Abstract: A focus ring for a plasma processing apparatus has an inner region (12a), middle region (12b), and outer region (12c), disposed in this order from the inner side to surround a target substrate (W). On the side to be exposed to plasma, the surfaces of the inner region (12a) and outer region (12c) consist essentially of a dielectric, while the surface of the middle region (12b) consists essentially of a conductor. The middle region (12b) is arranged to shift the peak of plasma density to the outside of the peripheral edge of the target substrate (W). If there is no middle region (12b), the peak of plasma density appears substantially directly above the peripheral edge of the target substrate (W).
    Type: Application
    Filed: August 15, 2003
    Publication date: April 22, 2004
    Inventors: Takaaki Nezu, Katsumi Horiguchi, Daisuke Hayashi, Toshiya Tsukahara