Patents by Inventor Katsumi Ikegaya

Katsumi Ikegaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006975
    Abstract: Provided is a power conversion device on which an IGBT power module that includes a main IGBT and a current sense IGBT in the same semiconductor chip is mounted, wherein the power conversion device is a high-performance and highly reliable power conversion device capable of accurately estimating a main current flowing through the main IGBT using a sense current in an entire operation region of the power conversion device. A power conversion device includes: a first IGBT through which a main current flows; a second IGBT which is disposed on the same semiconductor substrate as the first IGBT and through which a sense current flows; and a measurement device which calculates the main current based on the sense current, wherein the measurement device selects a method of calculating the main current corresponding to a current value of the sense current.
    Type: Application
    Filed: September 10, 2021
    Publication date: January 4, 2024
    Applicant: Hitachi Astemo, Ltd.
    Inventors: Katsumi IKEGAYA, Yoichiro KOBAYASHI
  • Patent number: 11587951
    Abstract: Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 21, 2023
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Takayuki Oshima, Katsumi Ikegaya, Masato Kita, Keishi Komoriyama, Kiyotaka Kanno, Shinichirou Wada
  • Patent number: 11417452
    Abstract: An object is to provide a new electronic control unit that can improve detection accuracy of a sense current even in a region where the current value of the sense current is small. Provided is a sense current detection unit including a plurality of sense transistors that have different current flow rates and that are connected to current output transistors controlling a current flowing in a coil load. The current in the sense current detection unit is input to an analog/digital converter, and the current value of the current flowing in the sense current detection unit is converted into a digital value. The current value of the current flowing in the sense current detection unit is increased through a combination or a selection of the plurality of sense transistors of the sense current detection unit in a region where the current value of the main current of the current output transistors is small compared to a region where the current value of the main current is large.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 16, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Katsumi Ikegaya, Keishi Komoriyama, Yoshiaki Mizuhashi, Takayuki Oshima, Shinichirou Wada
  • Publication number: 20220221891
    Abstract: In a semiconductor device including a current mirror circuit, a highly reliable semiconductor device that reduces a variation in a mirror ratio of the current mirror circuit and suppresses a change with time in a pairing property of elements can be provided.
    Type: Application
    Filed: May 15, 2020
    Publication date: July 14, 2022
    Applicant: Hitachi Astemo, Ltd.
    Inventors: Katsumi IKEGAYA, Yoichiro KOBAYASHI, Minoru MIGITA
  • Publication number: 20220020702
    Abstract: In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors.
    Type: Application
    Filed: November 27, 2019
    Publication date: January 20, 2022
    Inventors: Katsumi IKEGAYA, Takayuki OSHIMA, Yoichiro KOBAYASHI, Masato KITA, Keishi KOMORIYAMA, Minoru MIGITA, Yu KAWAGOE, Kiyotaka KANNO
  • Patent number: 11145646
    Abstract: Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 12, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou Wada, Katsumi Ikegaya
  • Publication number: 20210233935
    Abstract: Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy.
    Type: Application
    Filed: April 23, 2019
    Publication date: July 29, 2021
    Applicant: Hitachi Automotive Systems, Ltd.
    Inventors: Takayuki OSHIMA, Katsumi IKEGAYA, Masato KITA, Keishi KOMORIYAMA, Kiyotaka KANNO, Shinichirou WADA
  • Patent number: 11004762
    Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 11, 2021
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takayuki Oshima, Shinichirou Wada, Katsumi Ikegaya, Hiroshi Yoneda
  • Publication number: 20200227409
    Abstract: Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.
    Type: Application
    Filed: April 16, 2018
    Publication date: July 16, 2020
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou WADA, Katsumi IKEGAYA
  • Publication number: 20200211745
    Abstract: An object is to provide a new electronic control unit that can improve detection accuracy of a sense current even in a region where the current value of the sense current is small. Provided is a sense current detection unit including a plurality of sense transistors that have different current flow rates and that are connected to current output transistors controlling a current flowing in a coil load. The current in the sense current detection unit is input to an analog/digital converter, and the current value of the current flowing in the sense current detection unit is converted into a digital value. The current value of the current flowing in the sense current detection unit is increased through a combination or a selection of the plurality of sense transistors of the sense current detection unit in a region where the current value of the main current of the current output transistors is small compared to a region where the current value of the main current is large.
    Type: Application
    Filed: April 19, 2018
    Publication date: July 2, 2020
    Inventors: Katsumi IKEGAYA, Keishi KOMORIYAMA, Yoshiaki MIZUHASHI, Takayuki OSHIMA, Shinichirou WADA
  • Patent number: 10665496
    Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 26, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinichirou Wada, Takayuki Oshima, Katsumi Ikegaya
  • Patent number: 10403620
    Abstract: To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistor 101 is formed in a region S1 on the surface of a SOI substrate 30. A trench 41 surrounds the high-side NMOS transistor 101. SiO2 (first insulator) embeds the trench 41. A low-side NMOS transistor 102 is formed in a region S2 on the surface of the SOI substrate 30 around the trench 41. The side face Sf connecting the region S2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: September 3, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou Wada, Katsumi Ikegaya
  • Publication number: 20190043851
    Abstract: To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistor 101 is formed in a region S1 on the surface of a SOI substrate 30. A trench 41 surrounds the high-side NMOS transistor 101. SiO2 (first insulator) embeds the trench 41. A low-side NMOS transistor 102 is formed in a region S2 on the surface of the SOI substrate 30 around the trench 41. The side face Sf connecting the region S2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.
    Type: Application
    Filed: January 12, 2017
    Publication date: February 7, 2019
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou WADA, Katsumi IKEGAYA
  • Patent number: 10170415
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 1, 2019
    Assignee: Hitachi Automotive Systems, Inc.
    Inventors: Katsumi Ikegaya, Takayuki Oshima
  • Publication number: 20180247892
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 30, 2018
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Katsumi IKEGAYA, Takayuki OSHIMA
  • Publication number: 20180218936
    Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 2, 2018
    Inventors: Shinichirou WADA, Takayuki OSHIMA, Katsumi IKEGAYA
  • Publication number: 20180211898
    Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.
    Type: Application
    Filed: August 2, 2016
    Publication date: July 26, 2018
    Inventors: Takayuki OSHIMA, Shinichirou WADA, Katsumi IKEGAYA, Hiroshi YONEDA
  • Patent number: 7945410
    Abstract: An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: May 17, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Natsuyo Morioka, Seiji Ishikawa, Katsumi Ikegaya, Yasunori Yamaguchi, Kazuo Ito, Yuichi Hamamura
  • Publication number: 20080140330
    Abstract: An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
    Type: Application
    Filed: August 9, 2007
    Publication date: June 12, 2008
    Inventors: Natsuyo Morioka, Seiji Ishikawa, Katsumi Ikegaya, Yasunori Yamaguchi, Kazuo Ito, Yuichi Hamamura