Patents by Inventor Katsumi Ikegaya

Katsumi Ikegaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190043851
    Abstract: To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor. A high-side NMOS transistor 101 is formed in a region S1 on the surface of a SOI substrate 30. A trench 41 surrounds the high-side NMOS transistor 101. SiO2 (first insulator) embeds the trench 41. A low-side NMOS transistor 102 is formed in a region S2 on the surface of the SOI substrate 30 around the trench 41. The side face Sf connecting the region S2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.
    Type: Application
    Filed: January 12, 2017
    Publication date: February 7, 2019
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou WADA, Katsumi IKEGAYA
  • Patent number: 10170415
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 1, 2019
    Assignee: Hitachi Automotive Systems, Inc.
    Inventors: Katsumi Ikegaya, Takayuki Oshima
  • Publication number: 20180247892
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 30, 2018
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Katsumi IKEGAYA, Takayuki OSHIMA
  • Publication number: 20180218936
    Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 2, 2018
    Inventors: Shinichirou WADA, Takayuki OSHIMA, Katsumi IKEGAYA
  • Publication number: 20180211898
    Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.
    Type: Application
    Filed: August 2, 2016
    Publication date: July 26, 2018
    Inventors: Takayuki OSHIMA, Shinichirou WADA, Katsumi IKEGAYA, Hiroshi YONEDA
  • Patent number: 7945410
    Abstract: An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: May 17, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Natsuyo Morioka, Seiji Ishikawa, Katsumi Ikegaya, Yasunori Yamaguchi, Kazuo Ito, Yuichi Hamamura
  • Publication number: 20080140330
    Abstract: An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product. With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
    Type: Application
    Filed: August 9, 2007
    Publication date: June 12, 2008
    Inventors: Natsuyo Morioka, Seiji Ishikawa, Katsumi Ikegaya, Yasunori Yamaguchi, Kazuo Ito, Yuichi Hamamura