Abstract: The packet transmission device including: a first and a second storage module to store a token value; a token controller to add a predetermined token value to a first total token value, and subtract a predetermined token value from the first total value in response to the output of the packet; an overrun state controller to add an excess of the first total token value over a predetermined upper limit value to a second total token value, in the case where the first total token value added by addition control is greater than or equal to the predetermined upper limit value; and an underrun state controller to subtract a predetermined token value from the second total token value and add the subtracted token value to the first total token value, in the case where the subtracted first total token value is less than the predetermined upper limit value.

Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract: The packet transmission device including: a first and a second storage module to store a token value; a token controller to add a predetermined token value to a first total token value, and subtract a predetermined token value from the first total value in response to the output of the packet; an overrun state controller to add an excess of the first total token value over a predetermined upper limit value to a second total token value, in the case where the first total token value added by addition control is greater than or equal to the predetermined upper limit value; and an underrun state controller to subtract a predetermined token value from the second total token value and add the subtracted token value to the first total token value, in the case where the subtracted first total token value is less than the predetermined upper limit value.

Abstract: A packet relaying apparatus includes queues holding packet information, and queue control units controlling dequeueing. The dequeueing means transmission of packet information from a queue of a previous stage to a queue of a next stage. The packet relaying apparatus further includes a packet information control unit that, on receiving packet information to be dequeued at the time of dequeueing, returns discard information and data volume corresponding to the received packet information, a first bandwidth adjusting unit that, on determining that the received packet has been discarded, discards the packet information, maintains a usable bandwidth, and transfers the discard information and the data volume to the previous stage, and a second bandwidth adjusting unit that, on receiving the discard information and the data volume from the next stage, adds the data volume to the usable bandwidth and transfers the discard information and the data volume to a previous stage.

Abstract: A shaper circuit includes a storage part storing a current token, an add token, and a max token, a subtraction part subtracting a packet length of a dequeue target from the current token stored in the storage part and storing the current token in the storage part, an addition part adding the add token stored in the storage part to the current token stored in the storage part at constant periodic intervals and storing the current token in the storage part, a comparison part comparing the result of the addition with the max token stored in the storage part and preventing the addition result from exceeding the max token, and a determining part outputting a dequeue permission request. A number of bits in a decimal part of the current token are set and a number of bits in an integer part of the add token are set.

Abstract: When a ringlet with a high frame transfer quality is selected as a switching candidate for each station of a transfer destination from information on frame transfer quality for each ringlet, when it is determined that a fundamental ringlet is in a preceding stage of degradation of the frame transfer quality from information on the frame transfer quality of the fundamental ringlet, and if the fundamental ringlet is different from the switching candidate, a ringlet for transferring a frame to a station of the transfer destination is switched from the fundamental ringlet to the switching candidate.

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Abstract: A packet relaying apparatus includes queues holding packet information, and queue control units controlling dequeueing. The dequeueing means transmission of packet information from a queue of a previous stage to a queue of a next stage. The packet relaying apparatus further includes a packet information control unit that, on receiving packet information to be dequeued at the time of dequeueing, returns discard information and data volume corresponding to the received packet information, a first bandwidth adjusting unit that, on determining that the received packet has been discarded, discards the packet information, maintains a usable bandwidth, and transfers the discard information and the data volume to the previous stage, and a second bandwidth adjusting unit that, on receiving the discard information and the data volume from the next stage, adds the data volume to the usable bandwidth and transfers the discard information and the data volume to a previous stage.

Abstract: A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

Abstract: An Ethernet frame nester nests Ethernet frames addressed to a plurality of remote station devices affiliated with a shared station device on the basis of the correspondence relation between a MAC address of the station device and MAC addresses of the remote station devices stored in a table and the transmission destination addresses of the Ethernet frames. The Ethernet frame nester then converts them into an RPR frame. When receiving an RPR frame addressed to the own station device, an Ethernet frame extractor extracts Ethernet frames from the RPR frame and transmits each Ethernet frame to the addressed remote station devices.

Abstract: When a ringlet with a high frame transfer quality is selected as a switching candidate for each station of a transfer destination from information on frame transfer quality for each ringlet, when it is determined that a fundamental ringlet is in a preceding stage of degradation of the frame transfer quality from information on the frame transfer quality of the fundamental ringlet, and if the fundamental ringlet is different from the switching candidate, a ringlet for transferring a frame to a station of the transfer destination is switched from the fundamental ringlet to the switching candidate.

Abstract: A shaper circuit for controlling input packets using a token bucket algorithm is disclosed.

Abstract: A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

Abstract: A packet communication apparatus using a timer for always completing the transmission of a received packet within a delay assurance time length assurable by itself. The packet communication apparatus notifies information on the delay assurance time length to a destination side packet communication apparatus, while the destination side packet communication apparatus determines a received packet buffering quantity in communication with the origination side packet communication apparatus on the basis of the information notified. This optimizes a received packet buffering quantity in the destination side packet communication apparatus in a packet communication system, thus enabling the assurance of a necessary communication quality at a low cost.