Patents by Inventor Katsumi Morii
Katsumi Morii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10304830Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.Type: GrantFiled: June 8, 2018Date of Patent: May 28, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsumi Morii, Yoshitaka Otsu
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Publication number: 20180294265Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.Type: ApplicationFiled: June 8, 2018Publication date: October 11, 2018Inventors: Katsumi MORII, Yoshitaka OTSU
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Publication number: 20180240702Abstract: According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. A semiconductor body extends in the stacked body in a stacking direction of the stacked body. A charge storage portion is provided between the semiconductor body and one of the conductive layers. A silicon oxide film is provided between the charge storage portion and the one of the conductive layers. A silicon nitride film is provided between the silicon oxide film and the one of the conductive layers.Type: ApplicationFiled: September 5, 2017Publication date: August 23, 2018Applicant: Toshiba Memory CorporationInventor: Katsumi MORII
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Patent number: 10020305Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.Type: GrantFiled: February 21, 2017Date of Patent: July 10, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsumi Morii, Yoshitaka Otsu
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Publication number: 20170162572Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: Katsumi MORII, Yoshitaka OTSU
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Patent number: 9614076Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.Type: GrantFiled: August 10, 2014Date of Patent: April 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsumi Morii, Yoshitaka Otsu
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Publication number: 20150041960Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.Type: ApplicationFiled: August 10, 2014Publication date: February 12, 2015Inventors: Katsumi MORII, Yoshitaka OTSU
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Patent number: 8692352Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: GrantFiled: December 21, 2012Date of Patent: April 8, 2014Assignee: Renesas Electronics CorporationInventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
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Patent number: 8569839Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.Type: GrantFiled: January 20, 2011Date of Patent: October 29, 2013Assignee: Renesas Electronics CorporationInventors: Katsumi Morii, Yoshitaka Otsu, Kazuma Onishi, Tetsuya Nitta, Tatsuya Shiromoto, Shigeo Tokumitsu
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Patent number: 8357989Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: GrantFiled: September 15, 2010Date of Patent: January 22, 2013Assignee: Renesas Electronics CorporationInventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
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Publication number: 20110175205Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.Type: ApplicationFiled: January 20, 2011Publication date: July 21, 2011Inventors: Katsumi MORII, Yoshitaka OTSU, Kazuma ONISHI, Tetsuya NITTA, Tatsuya SHIROMOTO, Shigeo TOKUMITSU
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Publication number: 20110062547Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: ApplicationFiled: September 15, 2010Publication date: March 17, 2011Inventors: Kazuma ONISHI, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
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Patent number: RE46773Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: GrantFiled: April 7, 2016Date of Patent: April 3, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
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Patent number: RE48450Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.Type: GrantFiled: March 13, 2018Date of Patent: February 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii