Patents by Inventor Katsumi Ogiri

Katsumi Ogiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6784036
    Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding over an undercut in an underlying layer, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: August 31, 2004
    Assignees: Fujitsu Limited, Fujitsu Quantum Devices Limited
    Inventors: Kozo Makiyama, Katsumi Ogiri
  • Publication number: 20030207554
    Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
    Type: Application
    Filed: June 9, 2003
    Publication date: November 6, 2003
    Applicants: FUJITSU LIMITED, FUJITSU QUANTUM DEVICES LIMITED
    Inventors: Kozo Makiyama, Katsumi Ogiri
  • Patent number: 6620716
    Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: September 16, 2003
    Assignees: Fujitsu Limited, Fujitsu Quantum Devices Ltd.
    Inventors: Kozo Makiyama, Katsumi Ogiri
  • Publication number: 20030109098
    Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.
    Type: Application
    Filed: April 3, 2002
    Publication date: June 12, 2003
    Applicants: Fujitsu Limited, Fujitsu Quantum Devices Limited
    Inventors: Kozo Makiyama, Katsumi Ogiri
  • Patent number: 6509252
    Abstract: A method of manufacturing a semiconductor device includes an exposing step of transferring a support pattern onto an non-exposed area of a resist layer so that an opening for forming a support is formed in a thick part of the resist layer. The support is formed simultaneously with a gate electrode in a body using the resist layer having the opening. The gate electrode on a mesa extending into the outside of the mesa is supported by both a mesa layer and the support.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: January 21, 2003
    Assignees: Fujitsu Limited, Fujitsu Quantum Devices Ltd.
    Inventors: Kozo Makiyama, Katsumi Ogiri