Abstract: In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Abstract: A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

Abstract: A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.

Abstract: In a semiconductor device of the type in which a bipolar element and MOS field-effect transistors are formed on one surface of a semiconductor substrate, this invention discloses a semiconductor device characterized in that first buried layers of a first conductivity type are formed within regions of the semiconductor substrate in which the bipolar element are formed, a second buried layer of the first conductivity and at least one MOS field-effect transistor type is formed within the semiconductor substrate facing at least the emitter of the bipolar element, and the depth from one surface of the semiconductor substrate to the second buried layer of the first conductivity type is less than the depth from that surface to the first buried layer of the first conductivity type.This invention can prevent any increase in the capacity of the MOS field-effect transistor, and can also improve the operating speed of the bipolar element.

Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Abstract: A read-only memory has a terminal for receiving a writing current and a data input/output terminal. In the writing operation, the writing current is supplied to the terminal which is different from the data input/output terminal. Therefore, a data output circuit can be constituted by an ECL circuit having a relatively low withstand voltage, and a selection circuit related to the reading operation is achieved by using an ECL circuit. Accordingly, the read-only memory performs the reading operation at high speeds. During the writing operation, a different selection circuit is used which can withstand high voltages.

Abstract: A packaged semiconductor device structure includes a semiconductor chip with an organic material covering thereon. The semiconductor chip is placed in a package and hermetically sealed with a low melting point glass. The organic covering serve to suppress undesirable influence on the semiconductor chip by .alpha.-rays which may be radiated from the package, and a getter material is placed in the package for decreasing undesirable gases in the package which may be emitted by the organic covering during the sealing process.

Abstract: An I.sup.2 L device is disclosed wherein the P type injector region of a PNP transistor is formed so as to be buried in an N.sup.- type epitaxial layer below the P type collector region of the PNP transistor, whereby the carrier injection efficiency of the transistor is improved and a high switching speed is obtained. The I.sup.2 L device further includes an inversed NPN transistor wherein the abovementioned P type collector region of the PNP transistor works as a base region of the NPN transistor, an N type collector region is formed in the P type base region, and the abovementioned P type injector region extends between the N.sup.- type epitaxial layer and an N.sup.+ type substrate except below the N type collector region so that the effective emitter portion of the NPN transistor is limited to a specific area immediately below the N type collector region, thereby to reduce the power consumption.

Abstract: An I.sup.2 L device is disclosed wherein the P type injector region of a PNP transistor is formed so as to be buried in an N.sup.- type epitaxial layer below the P type collector region of the PNP transistor, whereby the carrier injection efficiency of the transistor is improved and a high switching speed is obtained. The I.sup.2 L device further includes an inversed NPN transistor wherein the abovementioned P type collector region of the PNP transistor works as a base region of the NPN transistor, an N type collector region is formed in the P type base region, and the abovementioned P type injector region extends between the N.sup.- type epitaxial layer and an N.sup.+ type substrate except below the N type collector region so that the effective emitter portion of the NPN transistor is limited to a specific area immediately below the N type collector region, thereby to reduce the power consumption.

Abstract: The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.