Abstract: A circuit device includes a charging circuit, an A/D conversion circuit, a control circuit, and a linear regulator circuit. The charging circuit supplies a charging current to a battery based on a power supply voltage. The A/D conversion circuit A/D-converts a battery voltage and outputs battery voltage data. The control circuit outputs voltage control data for controlling a voltage value of the power supply voltage based on the battery voltage data such that a difference between the power supply voltage and the battery voltage is a given set voltage. The linear regulator circuit supplies the power supply voltage to the charging circuit based on the voltage control data.

Abstract: A circuit device includes: a current source circuit; a first charging circuit; a second charging circuit; and a control circuit. The control circuit controls, when a current setting value is in a first current range, supply of a first charging current from the first charging circuit to a charging node. The control circuit controls, when the current setting value is in a second current range on a current side higher than the first current range, supply of a second charging current from the second charging circuit to the charging node. The control circuit sets both the first charging current and the second charging current to a non-supply state during a switching period between the first current mode and the second current mode.

Abstract: A circuit device includes: a current source circuit; a first charging circuit; a second charging circuit; and a control circuit. The control circuit controls, when a current setting value is in a first current range, supply of a first charging current from the first charging circuit to a charging node. The control circuit controls, when the current setting value is in a second current range on a current side higher than the first current range, supply of a second charging current from the second charging circuit to the charging node. The control circuit sets the current source control value such that the output current of the current source circuit is zero or is reduced during a switching period of the current source control value.

Abstract: A circuit device includes a current source circuit, a first charging circuit, a second charging circuit, and a control circuit. The control circuit supplies, when a current setting value is in a first current range, a first charging current of a current value indicated by a first setting value from the first charging circuit to a charging node. The control circuit supplies, when the current setting value is in a second current range, a second charging current of a current value indicated by a second setting value from the second charging circuit to the charging node. The control circuit performs at least one of first correction for correcting a first conversion characteristic and second correction for correcting a second conversion characteristic.

Abstract: An integrated circuit device includes a terminal, a switch circuit, an amplifier circuit, a voltage boosting circuit, and a control circuit. The terminal is connected to a driving signal line of a driving circuit that drives an actuator of a liquid droplet ejection head. One end of the switch circuit is connected to the terminal. The amplifier circuit receives an output signal from the other end of the switch circuit, and amplifies an induced voltage of the actuator after the actuator having been driven. The voltage boosting circuit generates a boosted voltage for level-shifting a switching signal of the switch circuit based on the step-up clock signal.

Abstract: When landing detection or removal detection for a power reception apparatus through intermittent power transmission is performed in a first channel and landing detection or removal detection for a power reception apparatus through intermittent power transmission is performed in a second channel, a control circuit controls a transmission timing of a second drive pulse in the intermittent power transmission of the second channel such that a first drive pulse in the intermittent power transmission of the first channel and the second drive pulse do not overlap.

Abstract: When landing detection or removal detection for a power reception apparatus through intermittent power transmission is performed in a first channel and landing detection or removal detection for a power reception apparatus through intermittent power transmission is performed in a second channel, a control circuit controls a transmission timing of a second drive pulse in the intermittent power transmission of the second channel such that a first drive pulse in the intermittent power transmission of the first channel and the second drive pulse do not overlap.

Abstract: An integrated circuit device includes a terminal, a switch circuit, an amplifier circuit, a voltage boosting circuit, and a control circuit. The terminal is connected to a driving signal line of a driving circuit that drives an actuator of a liquid droplet ejection head. One end of the switch circuit is connected to the terminal. The amplifier circuit receives an output signal from the other end of the switch circuit, and amplifies an induced voltage of the actuator after the actuator having been driven. The voltage boosting circuit generates a boosted voltage for level-shifting a switching signal of the switch circuit based on the step-up clock signal.

Abstract: A display control device includes a first interface unit that receives display information of a first display method that includes image data and a control information setting unit that sets control information used for controlling display of an image in the display unit in accordance with setting information that specifies a display method. The display control device further includes an image data conversion unit that converts, if a second display method is specified by the setting information, the image data of the first display method type to image data of the second display method type in accordance with the control information. The display control device also includes a second interface unit that outputs the image data of the first or the second display method type in accordance with the setting information, and outputs signals for controlling the display unit in accordance with the control information.

Abstract: A display control device includes a first interface unit that receives display information of a first display method that includes image data and a control information setting unit that sets control information used for controlling display of an image in the display unit in accordance with setting information that specifies a display method. The display control device further includes an image data conversion unit that converts, if a second display method is specified by the setting information, the image data of the first display method type to image data of the second display method type in accordance with the control information. The display control device also includes a second interface unit that outputs the image data of the first or the second display method type in accordance with the setting information, and outputs signals for controlling the display unit in accordance with the control information.

Abstract: An arbiter device for a multi-port memory is provided that includes an identical address detection circuit, an OR gate circuit, a D-type flip-flop, a buffer, and a selector. The identical address detection circuit can detect if input addresses to two ports of a multi-port memory are identical with each other. The selector outputs output data on the write port and output data on the read port. When an input address to the A port of the multi-port memory is identical with an input address to the B port thereof, the operation of the B port is stopped, and data on the A port is selected and output, such that simultaneous accesses to the same address can be made. As such, an arbiter device for a multi-port memory can be provided that enables simultaneous accesses to the same address when an input address to a first port of a multi-port memory and an input address to a second port of the multi-port memory are identical.

Abstract: A semiconductor memory is provided which has a FIFO memory in which data is read in synchronization with a read clock signal. In order to read the memory, the device has a read controller which generates a read counter clock signal in synchronization with the read clock signal and a memory read access signal, and which generates a read counter reset signal which becomes active in synchronization with the read clock signal after the reset signal becomes active. The device also has a read counter which sequentially generates first read addresses whose address values are different in synchronization with the read clock signal and is reset when the read counter reset signal is active, and an AND gate group in which second read address signals are output and first read address signals from a read counter and the reset signal are input.

Abstract: Fire retardant unsaturated polyester resin compositions are prepared by intimate mixing of unsaturated polyester resins and 100-900 parts by weight of hydrated magnesium carbonate per 100 parts by weight of polyester resin. Such compositions when reinforced with glass are suitable for use in building fire retardant interiors.

Abstract: Discloses a fluid aqueous suspension of magnesium hydroxide having a solid concentration between about 35 and 60 percent by weight and a viscosity up to 10,000 cp. comprising at least 0.5% by weight of a sodium naphthalenesulfonate surface active agent based on the weight of magnesium hydroxide.