Abstract: An automatic LVS rule file generation apparatus includes a definition file generating unit and a rule file generating unit. The definition file generating unit generates definition files used for a layout verification based on first data and templates that are used for the layout verification in a layout design of a semiconductor apparatus. The rule file generating unit automatically generates a LVS rule file based on the definition rule files. The templates includes first parameters indicating three-dimensional structures of the semiconductor apparatus. The definition files includes second data with respect to the first parameters.

Abstract: A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic evaluation of the semiconductor device. The semiconductor device comprises a lower-layer signal line provided below one of a main power-supply line and a main ground line via an insulating layer; and an upper-layer signal line provided above said one of the main power-supply line and the main ground line via an insulating layer. A window is formed in said one of the main power-supply line and the main ground line; and the lower-layer signal line and the upper-layer signal line are electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line.

Abstract: A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic evaluation of the semiconductor device. The semiconductor device comprises a lower-layer signal line provided below one of a main power-supply line and a main ground line via an insulating layer; and an upper-layer signal line provided above said one of the main power-supply line and the main ground line via an insulating layer. A window is formed in said one of the main power-supply line and the main ground line; and the lower-layer signal line and the upper-layer signal line are electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line.

Abstract: A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic evaluation of the semiconductor device. The semiconductor device comprises a lower-layer signal line provided below one of a main power-supply line and a main ground line via an insulating layer; and an upper-layer signal line provided above said one of the main power-supply line and the main ground line via an insulating layer. A window is formed in said one of the main power-supply line and the main ground line; and the lower-layer signal line and the upper-layer signal line are electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line.

Abstract: A first wiring layer is formed in a memory cell area on a semiconductor substrate. A first inter-layer insulating film for covering the first wiring layer is formed on the semiconductor substrate. A second wiring layer is formed in the memory cell area on the first inter-layer insulating film. A second inter-layer insulating film for covering the second wiring layer is formed on the first inter-layer insulating film. A signal wiring connected to at least of circuits in a peripheral circuit area is formed in a boundary area on the second inter-layer insulating film. A dummy wiring is formed of the same layer as the first wiring layer or the second wiring layer below the signal wiring.

Abstract: A first wiring layer is formed in a memory cell area on a semiconductor substrate. A first inter-layer insulating film for covering the first wiring layer is formed on the semiconductor substrate. A second wiring layer is formed in the memory cell area on the first inter-layer insulating film. A second inter-layer insulating film for covering the second wiring layer is formed on the first inter-layer insulating film. A signal wiring connected to at least of circuits in a peripheral circuit area is formed in a boundary area on the second inter-layer insulating film. A dummy wiring is formed of the same layer as the first wiring layer or the second wiring layer below the signal wiring.

Abstract: A semiconductor package which can prevent peeling of outer leads from solder caused by thermal expansion and contraction, after the semiconductor package is mounted on a printed wiring board, is disclosed. The semiconductor package according to this invention includes a resin sealed body having a semiconductor chip sealed therein and outer leads led out of the resin sealed body. The outer lead has a first and second inflection parts, and the outer lead includes a first portion which defines the segment from a lead-out part of the outer lead in the resin sealed body to the first inflection part, a second portion which defines the segment from the first inflection part to the second inflection part, and a third portion which defines the segment from the second inflection part to a terminating part of the outer lead. The length of the first portion is larger than the length of the third portion.