Patents by Inventor Katsumi Satoh

Katsumi Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299691
    Abstract: The semiconductor device includes: a transistor, and a body diode included in the transistor so that the body diode is anti-parallel to the transistor, and a diode anti-parallel connected to the bidirectional current-conduction device, wherein the bidirectional current-conduction device allows a first current and a second current to flow, and allows at least the second current to switch between conduction and non-conduction, the first current flowing in a first direction from a first main electrode of the transistor to a second main electrode facing the first main electrode, the second current flowing through the body diode in a second direction opposite to the first direction, and the diode is smaller in area than the bidirectional current-conduction device in a plan view.
    Type: Application
    Filed: December 30, 2022
    Publication date: September 21, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Publication number: 20230147438
    Abstract: A semiconductor device includes a layer structure including a first gate electrode and a second gate electrode, and a first main electrode and a second main electrode that can be electrically connected through the layer structure. The threshold voltage of the second gate electrode is higher than the threshold voltage of the first gate electrode. In the ? state and the ? condition, the switching operation is performed using the first gate electrode, and in the ? state or the ? condition, the switching operation is performed using the second gate electrode.
    Type: Application
    Filed: July 22, 2022
    Publication date: May 11, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Patent number: 11489066
    Abstract: The plurality of first control electrodes extend in a first direction in a planar view, the plurality of second control electrodes extend in a second direction in a planar view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate which faces the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or higher than 1.0.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Publication number: 20220149189
    Abstract: The plurality of first control electrodes extend in a first direction in a planar view, the plurality of second control electrodes extend in a second direction in a planar view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate which faces the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or higher than 1.0.
    Type: Application
    Filed: May 10, 2021
    Publication date: May 12, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Patent number: 11309386
    Abstract: Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 19, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Patent number: 11183588
    Abstract: A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 23, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Patent number: 11031491
    Abstract: A normally-off first gate channel region is provided on a first main surface side, in a region in a p base between an n base and an n emitter connected to an emitter electrode. On and off of the first gate channel region is controlled by a voltage of a first gate electrode. A normally-on second gate channel region is provided on a second main surface side, by an n-type region between an n collector electrically connected to a collector electrode and the n base. On and off of the second gate channel region is controlled by a voltage of a second gate electrode.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Publication number: 20210151562
    Abstract: Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.
    Type: Application
    Filed: September 8, 2020
    Publication date: May 20, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Publication number: 20210057555
    Abstract: A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.
    Type: Application
    Filed: January 28, 2020
    Publication date: February 25, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Patent number: 10840365
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: November 17, 2020
    Assignees: Kyushu Institute of Technology, Mitsubishi Electric Corporation, Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Katsumi Satoh, Tomoko Matsudai
  • Patent number: 10720918
    Abstract: Each of a P-side IGBT and an N-side IGBT connected in series to implement an arm includes a first gate and a second gate. In each of a drive circuit unit configured to control a voltage of the first gate with respect to a collector of the P-side IGBT, a drive circuit unit configured to control a voltage of the second gate with respect to an emitter of the P-side IGBT, and a drive circuit unit configured to control a voltage of the second gate with respect to a collector of the N-side IGBT, a signal processing circuit and an output circuit are electrically isolated from each other by an isolation structure.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Publication number: 20200112307
    Abstract: Each of a P-side IGBT and an N-side IGBT connected in series to implement an arm includes a first gate and a second gate. In each of a drive circuit unit configured to control a voltage of the first gate with respect to a collector of the P-side IGBT, a drive circuit unit configured to control a voltage of the second gate with respect to an emitter of the P-side IGBT, and a drive circuit unit configured to control a voltage of the second gate with respect to a collector of the N-side IGBT, a signal processing circuit and an output circuit are electrically isolated from each other by an isolation structure.
    Type: Application
    Filed: September 3, 2019
    Publication date: April 9, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Publication number: 20200098902
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Application
    Filed: December 9, 2017
    Publication date: March 26, 2020
    Inventors: Ichiro OMURA, Katsumi SATOH, Tomoko MATSUDAI
  • Publication number: 20200098903
    Abstract: A normally-off first gate channel region is provided on a first main surface side, in a region in a p base between an n base and an n emitter connected to an emitter electrode. On and off of the first gate channel region is controlled by a voltage of a first gate electrode. A normally-on second gate channel region is provided on a second main surface side, by an n-type region between an n collector electrically connected to a collector electrode and the n base. On and off of the second gate channel region is controlled by a voltage of a second gate electrode.
    Type: Application
    Filed: July 10, 2019
    Publication date: March 26, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Katsumi SATOH
  • Patent number: 7012332
    Abstract: A semiconductor chip and connection ends of corresponding external electrode terminals are encapsulated with a glass based sealing material, and the semiconductor chip includes a wide gap semiconductor element, and the electrodes of the semiconductor chip are connected to the end portions of the external electrode terminals by a silver based brazing member and/or pressure contact.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: March 14, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukitaka Hori, Katsumi Satoh, Norihisa Asano
  • Patent number: 6832549
    Abstract: A rotary printing press includes a plurality of printing units, including at least one multiple-printing unit having a plurality of printing devices arranged vertically in layers. A plurality of first web feed units each having a web roll support device are provided for the printing units in one-to-one correspondence. At least one second web feed unit having a web roll support device is provided as a counterpart to the first web feed unit corresponding to the multiple-printing unit. The printing press includes a web roll transport apparatus, which includes a web roll transport path provided in between the first web feed units and the second web feed unit and along the row of printing units, and a web roll transport device traveling along the web roll transport path.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 21, 2004
    Assignee: Tokyo Kikai Seisakusho, Ltd.
    Inventor: Katsumi Satoh
  • Publication number: 20040206258
    Abstract: A rotary printing press includes a plurality of printing units, including at lease one multiple-printing unit having a plurality of printing devices arranged vertically in layers. A plurality of first web feed units each having a web roll support device are provided for the printing units in one-to-one correspondence. At least one second web feed unit having a web roll support device is provided as a counterpart to the first web feed unit corresponding to the multiple-printing unit. The printing press includes a web roll transport apparatus, which includes a web roll transport path provided in between the first web feed units and the second web feed unit and along the row of printing units, and a web roll transport device traveling along the web roll transport path.
    Type: Application
    Filed: November 12, 2003
    Publication date: October 21, 2004
    Applicant: TOKYO KIKAI SEISAKUSHO LTD.
    Inventor: Katsumi Satoh
  • Publication number: 20040070059
    Abstract: A semiconductor chip and connection ends of corresponding external electrode terminals are encapsulated with a glass based sealing material, and the semiconductor chip includes a wide gap semiconductor element, and the electrodes of the semiconductor chip are connected to the end portions of the external electrode terminals by a silver based brazing member and/or pressure contact.
    Type: Application
    Filed: September 25, 2003
    Publication date: April 15, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yukitaka Hori, Katsumi Satoh, Norihisa Asano
  • Patent number: 6696702
    Abstract: An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor (12) is connected in parallel to a diode (11) made of silicon carbide. Although a resistive component of the diode (11) varies widely with turn-on and turn-off of the diode (11), connecting the resistor (12) in parallel to the diode (11) allows suppression of variations in a resistive component of an LCR circuit formed by the diode (11) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: February 24, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Satoh, Youichi Ishimura, Hideki Haruguchi
  • Patent number: 6670687
    Abstract: A semiconductor device having a silicon carbide layer of a singular conductivity type. The silicon carbide layer includes a surface having a first region, a second region, and a third region sandwiched between the first region and the second region. An anode electrode having a Schottky contact with the first region, a cathode electrode having an ohmic contact with the second region, and a control electrode having a Schottky contact with the third region are included in the semiconductor device.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: December 30, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Satoh, Shinichi Ishizawa