Patents by Inventor Katsumi Sugawara

Katsumi Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9059010
    Abstract: A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: June 16, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Masanori Yoshida, Katsumi Sugawara
  • Patent number: 8294281
    Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A supporting substrate is prepared. The supporting substrate has a chip mounting area, and a plurality of penetrating slits around the chip mounting area. At least a stack of semiconductor chips is formed over the chip mounting area. A first sealing member is formed, which seals the stack of semiconductor chips without the first sealing member filling the plurality of penetrating slits.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: October 23, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Masanori Yoshida, Katsumi Sugawara
  • Patent number: 8274143
    Abstract: A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: September 25, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujishima, Keiyo Kusanagi, Katsumi Sugawara, Koichi Hatakeyama
  • Publication number: 20120098145
    Abstract: A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 26, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Masanori Yoshida, Katsumi Sugawara
  • Publication number: 20100258931
    Abstract: A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 14, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Masanori Yoshida, Katsumi Sugawara
  • Publication number: 20100258932
    Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A supporting substrate is prepared. The supporting substrate has a chip mounting area, and a plurality of penetrating slits around the chip mounting area. At least a stack of semiconductor chips is formed over the chip mounting area. A first sealing member is formed, which seals the stack of semiconductor chips without the first sealing member filling the plurality of penetrating slits.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 14, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Masanori Yoshida, Katsumi Sugawara
  • Publication number: 20100258933
    Abstract: A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 14, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroyuki Fujishima, Keiyo Kusanagi, Katsumi Sugawara, Koichi Hatakeyama
  • Publication number: 20090189297
    Abstract: To provide a semiconductor device having high reliability by reducing the bending of a semiconductor device and mitigating stress exerted on external terminals. In a semiconductor device 1 having a semiconductor chip 9 mounted on a wiring substrate 2 comprising a base member 3 having a predetermined conductive pattern formed on both surfaces, slits 8 that penetrate the base member 3 in the vertical direction of the base member 3 are provided. When the semiconductor chip 9 and a wire 12 are sealed with resin, the same resin is used to fill the slits 8.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Inventors: Katsumi Sugawara, Fumitomo Watanabe