Abstract: An image processing device includes signal processors, a second-control-signal generator that generates second control signals in accordance with first control signals generated by the signal processors, and an image synthesizer. Each signal processor includes a first digital processor for performing image adjustment and a second digital processor. The second digital processor includes a defect detector that detects a defective pixel and a defective pixel adaptation processor that generates, in accordance with the result of defective pixel detection, the first control signal specifying a synthesis coefficient to the second-control-signal generator. In accordance with synthesis coefficients indicated by the second control signals, the image synthesizer synthesizes images that have undergone the image adjustment by the first digital processors of the signal processors.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A generator generates a visible light video signal by receiving visible light and generating an invisible light video signal by receiving invisible light. A synthesizer synthesizes the visible light video signal and the invisible light video signal in such a manner that a synthesis ratio can be changed. An adjuster receives parameters relating to image synthesis inputted by an operator from outside and adjusts the synthesis ratio based on the received parameters. A display unit generates a synthetic image from a synthetic video signal and displays the synthetic image. Then, the parameters inputted to the adjuster by the operator are received and the synthesis ratio is changed by the adjuster based on the received parameters while the synthetic image is being displayed by the display unit.

Abstract: An image signal processing circuit according to the present invention comprises an image signal processing unit, a line memory, a logic unit, an output pad and a data replacing unit. The image signal processing unit generates image data from an inputted image signal. The line memory temporarily memorizes the image data per line and outputs the memorized image data while switching to and from effective and ineffective. The logic unit generates digitally processed image data by digitally processing the image data outputted from the line memory. The output pad outputs the digitally processed image data. The data replacing unit generates dummy data and replaces data in a data region set as ineffective by the line memory among the image data outputted from the line memory or the digitally processed image data outputted from the logic unit with the dummy data.

Abstract: From horizontal and vertical coordinate values HC and VC of a pixel, a distance operation unit calculates a distance value RV indicating the distance from an optical-axis position to the pixel. A correction-data operation unit receives the distance value RV, and calculates correction data CD for the pixel by referring to an approximation function indicating relation between distance values and correction data. The approximation function is divided into a plurality of segments, and in each segment represented by a quadratic function defined by a predetermined number of sample points.

Abstract: An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group (110) is fed with data outputted from a flip-flop circuit group (106), adjusts a delay of the data so as to synchronize the operation of a data output terminal group (114) with the operation of a logic circuit (100), and outputs the data to the data output terminal group (114). A clock delay adjustment circuit (109) similarly adjusts a delay of a clock outputted from an inverter (105) and outputs the clock to a clock output terminal (113). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit (100) while keeping the phase relationship between an external output clock and external output data.

Abstract: In a filter correction circuit for a camera system according to the present invention, a sample area information detector detects frequency band and fluctuation level of a video signal by a unit of sample area where a screen is divided into a plurality of areas. A filter area information detector detects the frequency band and fluctuation level of the video signal by a unit of filter area that is a subject of one-time filter processing in the single screen. A filter condition switching judgment device generates a selection control signal based on the result detected by the sample area information detector. A selector selects a filter coefficient to be applied based on the selection control signal. A filter processor fetches the filter coefficient selected by the selector, from a filter coefficient register, and applies it to the pixel unit or smallest pixel group unit that corresponds to the filter coefficient.

Abstract: An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group (110) is fed with data outputted from a flip-flop circuit group (106), adjusts a delay of the data so as to synchronize the operation of a data output terminal group (114) with the operation of a logic circuit (100), and outputs the data to the data output terminal group (114). A clock delay adjustment circuit (109) similarly adjusts a delay of a clock outputted from an inverter (105) and outputs the clock to a clock output terminal (113). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit (100) while keeping the phase relationship between an external output clock and external output data.

Abstract: An image signal processing circuit according to the present invention comprises an image signal processing unit, a line memory, a logic unit, an output pad and a data replacing unit. The image signal processing unit generates image data from an inputted image signal. The line memory temporarily memorizes the image data per line and outputs the memorized image data while switching to and from effective and ineffective. The logic unit generates digitally processed image data by digitally processing the image data outputted from the line memory. The output pad outputs the digitally processed image data. The data replacing unit generates dummy data and replaces data in a data region set as ineffective by the line memory among the image data outputted from the line memory or the digitally processed image data outputted from the logic unit with the dummy data.

Abstract: A contour emphasizing circuit according to the present invention comprises a line memory circuit 11 for retaining image data of each scanning line, an image data retaining circuit 12 comprised of a combination of delay elements for delaying the image data per pixel, a contour emphasizing signal generating circuit 13 for executing a coefficient operation with respect to a central pixel and peripheral pixels and generating a contour emphasizing signal S2, an image boundary detecting circuit 14 for detecting an image boundary portion separating effective and ineffective of the image data, and an input/output switching circuit 15 for switching between an input to the image data retaining circuit 12 from the line memory circuit 11 and an output of the image data retaining circuit with respect to the contour emphasizing signal generating circuit 13 based on a result of the detection of the image boundary detecting circuit 14.

Abstract: From horizontal and vertical coordinate values HC and VC of a pixel, a distance operation unit calculates a distance value RV indicating the distance from an optical-axis position to the pixel. A correction-data operation unit receives the distance value RV, and calculates correction data CD for the pixel by referring to an approximation function indicating relation between distance values and correction data. The approximation function is divided into a plurality of segments, and in each segment represented by a quadratic function defined by a predetermined number of sample points.

Abstract: A flicker detecting apparatus has integrating means for integrating a pixel level every line in one frame or one field of a video to calculate a line lightness value, extracting means for extracting a fluctuation cycle in a vertical scanning direction of the line lightness value, and deciding means for deciding that a flicker is present when the fluctuation cycle is within a predetermined frequency range. The extracting means calculates a difference made by a fluctuation in the vertical scanning direction of the line lightness value every line, counts the number of continuations of an identical code in the difference, and calculates the count value as fluctuation cycle.

Abstract: Improvement is obtained in quality of transmitting by extraction of the accurate transfer data from the Symbol data stream includes Guard Interval and transfer data. The first aspect of the present invention is expansion of the size of the memory means for inputting to be able to store N+n samples (N means the size of symbol data, n is smaller than GI) using means to input the discrete input data sampled at a constant period, and fetch N samples of data from the optimum position. In the second aspect, the size of memory block for inputting stores N samples (N is power of 2, and N means the size of symbol data) as not changing their size. For inputting, at least 2 memory blocks are allocated with the function to independently control the riming to initiate fetching the input data to the each block. Therefore the data at the optimum position can be selected at the operation.

Abstract: In a cellular mobile telecommunications system, upon a hand-off request signal generated by a mobile station, the base station control office transfers traffic data to both the base station to which the mobile station is presently connected and another base station to which the present base station is adjacent. A hand-off order message is transferred from the present base station toward the mobile station. The control office is adapted to control the adjacent base station to transmit the hand-off order message if it fails to receive a hand-off confirmation from the mobile station.

Abstract: A radio phone equipment for credit card is adapted to transfer part or a whole of credit card or charge card information read by a card reader as well as a dial number dialed by a key pad to a mobile telecommunication switching office by means of a modem and a transmitter/receiver, and in case of said credit card or charge card being valid, switching, on the basis of a designation on a voice channel transmitted from said mobile telecommunication switching office, or transmitting and receiving frequency to said voice channel to construct a speech channel, and furthermore detecting on-hook of a handset produced upon finishing talking to reset the equipment.